參數(shù)資料
型號： TVP3010M
廠商： Texas Instruments, Inc.
英文描述： Video Interface Palette
中文描述： 視頻接口面板
文件頁數(shù)： 45/90頁
文件大?。?/td> 491K
代理商： TVP3010M
2–29
NOTE:
The multiplex mode is set by multiplexer control registers 1 and 2. When VGA
switching is desired, multiplexer control register 2 bit 7 must be set to 1 to enable
the VGA port and the desired direct-color mode must be chosen with the remaining
MCR bits. For example, when direct-color mode 1 is chosen and multiplexer control
register 2 is normally set to 1B (hex), for VGA switching it would instead be set to
9B (hex).
The DAC output is undefined if switch = 1 when doing overlay switching in a
direct-color mode that does not have overlay capability. When switching between
direct color and VGA, any direct-color mode may be chosen as long as the multiplex
ratio is 1:1.
Auxiliary-control register bits ACR2 and ACR1 can be used to independently
enable or disable the port-select and windowing functions as shown in the
equation 1. If both switching functions are disabled, ACR0 is used to default the
display to either direct color or palette graphics. Palette graphics are either VGA
or overlay when in a direct-color mode or pseudo-color when in the pseudo-color
mode. The reset default is for palette graphics to be displayed as needed for the
VGA pass-through mode.
All of the switching modes that involve overlay and direct color support the multiple
multiplexing ratios or LCLK divide ratios specified in subsection 2.4.3 and Table 2–6
for those modes supporting overlay. However, caution must be observed when
using the port-select function with the multiplexing modes other than 1:1 since the
PSEL signal is latched on LCLK (same as the pixel port).
The windowing functions can be performed using self-clocked or externally-
clocked frame-buffer interface timing (see subsection 2.3.2). When VGA switching
is involved, CLK0 is the main clock source since VGA-port data is latched on the
rising edge of this signal. Self-clocked timing can be used by externally connecting
RCLK to LCLK; however, this method is limited to a pixel rate of 50 MHz due to the
delay from CLK0 to RCLK. Externally clocked timing references all pixel data
latching to CLK0 by externally connecting CLK0 to LCLK. In both cases, the internal
circuit pipeline delay is adjusted so that the VGA and pixel-port data are
synchronous in time.
The use of the auxiliary window to display a VGA window in a direct-color background can be accomplished
by setting ACR2 = ACR0 = 0 and ACR1 = MCR2 bit 7 = 1 and is illustrated in Figure 2–10. The user can
also configure the auxiliary window to display direct color in the auxiliary window and VGA everywhere else
by setting ACR0 = 1 (not shown). Similarly, the auxiliary window can be configured to display overlay in the
window or outside of the window by setting MCR2 bit 7 = 0 (not shown).
Window Start (X, Y)
ééééééééééé
ééééééééééé
ééééééééééé
ééééééééééé
ééééééééééé
ééééééééééé
ééééééééééé
ééééééééééé
Figure 2–10. VGA in the Auxiliary Window
Direct Color
Auxiliary Window
Window Stop (X, Y)
相關(guān)PDF資料
PDF描述
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