參數(shù)資料
型號： TVP3010M
廠商： Texas Instruments, Inc.
英文描述： Video Interface Palette
中文描述： 視頻接口面板
文件頁數(shù)： 54/90頁
文件大小： 491K
代理商： TVP3010M
2–38
When external SFLAG logic is designed as an R–S latch that is set by split shift register transfer timing and
reset by SYSBL going high, the delay from SYSBL high to SFLAG low cannot exceed one-half of one SCLK
cycle. Otherwise, the SCLK generation logic could fail.
When the SSRT function is enabled but SFLAG is held low, the SCLK runs as if the SSRT function is
disabled. Since the SFLAG input is not qualified by the Blank signal within the palette, it needs to be held
low or disabled any time the SSRT SCLK pulse is not intended (see Section 2.3 and Figures 2–2 through
2–5 for more system details).
2.16 Control Register Definitions
The following paragraphs describe the operation of the TVP3010 control register.
2.16.1
The configuration register (see Table 2–19) controls the dual-function terminals on the TVP3010C or
TVP3010M to maintain pin compatibility with the TLC3407x VIP parts. At reset, the configuration register
defaults to TLC3407x compatible-pin settings. Bit 7 of the configuration register corresponds to data-bus
bit 7, index = 1E (hex).
Configuration Register
Table 2–19. Configuration Register
BIT
NAME
VALUES
DESCRIPTION
CR7
X
Reserved undefined
Reserved, undefined
CR6
0: In phase (default)
VCLK polarity select specifies whether the VCLK signal is in phase or opposite
phase of the RCLK and SCLK signals.
1: Opposite phase
CR5
0: Internal RCLK (default)
LCLK source selects the LCLK source. When bit 5 = 0, (default) LCLK is
internally connected to RCLK. When bit 5 = 1, CLK4[LCLK] is configured as the
LCLK input and an external LCLK source must be supplied (see
subsection 2.3.1).
1: CLK4[LCLK]
CR4
0: Disabled (default)
RCLK enable specifies whether RCLK is output on CLK3[RCLK]. When RCLK
is disabled, then CLK3[RCLK] is CLK3 (see Section 2.3).
1: Enabled
CR3
0: MUXOUT (default)
MUXOUT or SENSE selects MUXOUT or SENSE on MUXOUT[SENSE] (see
Sections 2.9 and 2.10).
1: SENSE
CR2
0: Low (default)
MUXOUT level terminal. When configuration register-bit CR3 = 0, then
MUXOUT level terminal. When configuration register bit CR3 0, then
MUXOUT controls the logic level on MUXOUT [SENSE].
1: High
CR1
0: 8/6 (default)
8/6 or OVS defines the terminal as 8/6 or OVS and controls the source of the
8/6 function signal. When CR1 = 0, then 8/6[OVS] is configured as the 8/6
terminal. When CR1 = 1, then CR0 controls the 8/6 function and is configured
as OVS (see Sections 2.1 and 2.7).
1: OVS
CR0
0: 6-bit (default)
8/6 level When CR1
8/6 level. When CR1 = 1, CR0 controls the 8/6 operation (see Section 2.1).
1 CR0 controls the 8/6 operation (see Section 2 1)
1: 8-bit (high)
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