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參數(shù)資料
| 型號： | TVP3010M |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | Video Interface Palette |
| 中文描述： | 視頻接口面板 |
| 文件頁數(shù)： | 34/90頁 |
| 文件大?。?/td> | 491K |
| 代理商： | TVP3010M |
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2–18
Table 2–7. Pseudo-Color Mode Pixel-Latching Sequence (see Notes 14 and 16)
v1
s1
P0
s2
P0
s3
P0
s4
P0
s6
s7
s8
VGA7–VGA0
P1, P0
P1–P0
P1–P0
P1
P1
P1
P1
P3, P2
P3–P2
P3–P2
P2
P2
P7
P2
P15
P2
P31
P5–P4
P5–P4
P15–P14
P3
P7–P6
s9
s11
s12
P3–P0
s13
P3–P0
s14
P3–P0
s16
P7–P0
s17
P7–P0
s18
P7–P0
P1–P0
P3–P0
P3–P2
P7–P4
P7–P4
P7–P4
P15–P8
P15–P8
P5–P4
P31–P30
NOTES: 14. The latching sequence is initiated by a rising edge on LCLK. For modes in which multiple groups of data
are latched, the LCLK rising edge latches all the groups and the pixel clock shifts them out starting with the
low-numbered group. For example, in pseudo-color submode 3 with a 16-bit pixel-bus width, the rising edge
of LCLK latches all the data groups shown above (s13) and the pixel clock shifts them out in the order
P(3–0), P(7–4), P(11–8), and P(15–12). Note that each line in each subtable above represents one pixel.
15. When in the big-endian format (GCR3 =1), the pixel bus is externally swapped by the user (i.e., D31
connected to P0, D0 connected to P31). Since data is always shifted out from low-numbered groups to
high-numbered groups, the external swapping of the pixel bus causes the groups to be shifted out in the
correct order. However, for modes with more than 1 bit per pixel, the bits in each data group are reversed
(LSB to MSB). This is internally corrected by the VIP input multiplexer. The differences between big- and
little-endian data formats and how they affect the pixel bus operation is discussed in more detail in
Appendix C.
P11–P8
P11–P8
P31–P28
P23–P16
P15–P12
P31–P24
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相關代理商/技術參數(shù) |
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| TVP3020 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:Video Interface Palette |
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| TVP3020-175PCE | 制造商:TI 制造商全稱:Texas Instruments 功能描述:Video Interface Palette |
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