參數(shù)資料
型號： TVP3020-135
廠商： Texas Instruments, Inc.
英文描述： Video Interface PALETTE(視頻接口調(diào)色器)
中文描述： 視頻接口盒（視頻接口調(diào)色器）
文件頁數(shù)： 12/98頁
文件大?。?/td> 582K
代理商： TVP3020-135
1–6
1.5
Terminal Functions (Continued)
PIN
NAME
NO.
I/O
DESCRIPTION
HSYNCOUT
61
O
(TTL
compatible)
Horizontal sync output after pipeline delay. For system mode the output
can be programmed, but for the VGA mode the output carries the same
polarity as the input.
Analog current outputs. These outputs can drive a 37.5-
load directly
(doubly terminated 75-
line), thus eliminating the requirement for any
external buffering.
IOR, IOG,
IOB
64, 66, 68
O
I/O0–I/O4
52–56
I/O
(TTL
compatible)
Software programmable I/O terminals that can be used to control
external devices.
LCLK
109
I
(TTL
compatible)
Pixel-port-latch clock input. LCLK is used to latch pixel-bus-input data.
OVS
86
I
(TTL
compatible)
Overscan input. OVS is used to create custom screen borders.
PSEL
87
I
(TTL
compatible)
Port select. PSEL provides the capability of VGA or overlay windows in
a direct color background on a pixel-by-pixel basis.
P0–P63
1–14, 17–36,
100–106,
113–121,
124–127,
135–144
I
(TTL
compatible)
Pixel input port. The port can be used in various modes as shown in the
multiplexer control register. All the unused terminals need to be tied to
GND.
RCLK
110
O
(TTL
compatible)
Reference clock output. RCLK is essentially the same as the SCLK
output but not gated off during blank. It can be used for pixel-port timing
reference or other system synchronization.
REF
72
Voltage reference for DACs. An internal voltage reference of nominally
1.235 V is provided, which requires an external 0.1-
μ
F ceramic
capacitor between REF and analog GND. However, the internal
reference voltage can be overdriven by an externally supplied
reference voltage. Typical connection is shown in Appendix A.
RESET
RD
57
38
I
I
Chip reset. All the registers default to the VGA mode after reset.
Read strobe input. A logic 0 on this terminal initiates a read from the
register map. Reads are performed asynchronously and are initiated on
the low-going edge of RD (see Figure 3–1).
(TTL
compatible)
RS0–RS2
49–51
I
(TTL
compatible)
Register select inputs. These terminals specify the location in the
register map that is to be accessed (see Table 2–1).
SCLK
112
O
(TTL
compatible)
Shift clock output. SCLK is selected as a division of the dot clock input.
The output signals are gated off during blank, although SCLK is still
used internally to synchronize with the activation of BLANK.
SENSE
58
O
(TTL
compatible)
Test mode DAC comparator output signal. This terminal is low if one or
more of the DAC output analog levels is above the internal comparator
reference of 350 mV
±
50 mV.
NOTE: All unused inputs should be tied to a logic level and not be allowed to float.
相關PDF資料
PDF描述
TVP3025-135 Video Interface PALETTE(三PLL，視頻接口調(diào)色器)
TVP3025-175 Video Interface PALETTE(三PLL，視頻接口調(diào)色器)
TVP3030-175 Video Interface PALETTE Exract(1600×1200，24位真彩色視頻接口調(diào)色器)
TVP3030-220 Video Interface PALETTE Exract(1600×1200，24位真彩色視頻接口調(diào)色器)
TVP3030-250 Video Interface PALETTE Exract(1600×1200，24位真彩色視頻接口調(diào)色器)
相關代理商/技術參數(shù)
參數(shù)描述
TVP3020-135MDN 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Texas Instruments 功能描述:
TVP3020-135PCE 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Texas Instruments 功能描述:
TVP3020-175MDN 制造商:TI 制造商全稱:Texas Instruments 功能描述:Video Interface Palette
TVP3020-175PCE 制造商:TI 制造商全稱:Texas Instruments 功能描述:Video Interface Palette
TVP3020-200MDN 制造商:Rochester Electronics LLC 功能描述:- Bulk
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