參數(shù)資料
型號： TVP3020-135
廠商： Texas Instruments, Inc.
英文描述： Video Interface PALETTE(視頻接口調(diào)色器)
中文描述： 視頻接口盒（視頻接口調(diào)色器）
文件頁數(shù)： 25/98頁
文件大?。?/td> 582K
代理商： TVP3020-135
2–11
VCLK
In Phase
SYSBL
at Input Terminal
LD
Internal Delayed
LCLK = RCLK
BLNK
(internal signal
before DOTCLK
pipeline delay)
PIXEL DATA
at Input Terminal
SCLK
Latch Last Group
of Pixel Data
Latch First Group of Pixel Data
2nd
Group
3rd
Group
4th
Group
5th
Group
6th
Group
First Group of Pixel Data
7th
Group
Last
Group
Latch Second Group
of Pixel Data
SCLK Between Split Shift Register Transfer and Regular Shift Register Transfer
SFLAG Input
Figure 2–5. SCLK/VCLK Control Timing
(SSRT Enabled, RCLK/SCLK Frequency = 4 x VCLK Frequency)
Multiplexing Scheme
The Viewpoint palette offers a highly versatile multiplexing scheme as illustrated in Tables 2–6 through 2–11.
The multiplexing scheme allows the pixel bus to be programmed to 1, 2, 4, 8, 12, 16, 24, or 32 bits/pixel with
pixel bus widths ranging from 1 bit to 64 bits. The use of on-chip multiplexing allows graphics systems to
be designed that can support multiple pixel depths and resolutions with no hardware modification. It also
allows the system to be configured to the amount of RAM available. For example, if only 256K bytes of
memory are available, an 800-by-600 mode with 4 bit planes (four bits per pixel) could be implemented using
an 8-bit-wide pixel bus. If at a later date another 256K bytes are added to another 8 bits of the pixel bus,
the user has the option of using 8 bit planes at the same resolution or 4 bit planes at a 1024 by 768 resolution.
When a further 512K bytes are added to the remaining 16 bits of the pixel bus, the user has the option of
8 bit planes at 1024 by 768 or 4 bit planes at 1280 by 1024. The Viewpoint palette can also be configured
for direct-color or true-color operation. All of the above could be achieved without any board-level hardware
modification and without any increase in the speed of the pixel bus.
2.4
Multiplexing of the pixel bus is controlled by and programmed through multiplex-control registers 1 and 2.
Table 2–6 details the multiplex-control register settings for each mode of operation (see also Sections 2.4.2
through 2.4.6).
2.4.1
The Viewpoint pixel bus supports both little- and big-endian data formats for all pseudo-color, direct-color,
and true-color modes of operation. The data-format select is controlled by general-control register bit 3 (see
Section 2.16.1). When general-control register (GCR) bit 3 is set to 0 (default), then the format is set to little
endian. When GCR bit 3 is set to 1, then the format is set to big endian.
Little-Endian and Big-Endian Data Format
In a big-endian design, the external VRAM data bus bits must be connected in reverse order to the Viewpoint
pixel bus; i.e., D63 connected to P0, D0 connected to P63, etc. This ensures that the least significant channel
相關(guān)PDF資料
PDF描述
TVP3025-135 Video Interface PALETTE(三PLL，視頻接口調(diào)色器)
TVP3025-175 Video Interface PALETTE(三PLL，視頻接口調(diào)色器)
TVP3030-175 Video Interface PALETTE Exract(1600×1200，24位真彩色視頻接口調(diào)色器)
TVP3030-220 Video Interface PALETTE Exract(1600×1200，24位真彩色視頻接口調(diào)色器)
TVP3030-250 Video Interface PALETTE Exract(1600×1200，24位真彩色視頻接口調(diào)色器)
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
TVP3020-135MDN 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Texas Instruments 功能描述:
TVP3020-135PCE 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Texas Instruments 功能描述:
TVP3020-175MDN 制造商:TI 制造商全稱:Texas Instruments 功能描述:Video Interface Palette
TVP3020-175PCE 制造商:TI 制造商全稱:Texas Instruments 功能描述:Video Interface Palette
TVP3020-200MDN 制造商:Rochester Electronics LLC 功能描述:- Bulk
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