- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄385951 > TVP3020-135 (Texas Instruments, Inc.) Video Interface PALETTE(視頻接口調(diào)色器) PDF資料下載
參數(shù)資料
| 型號： | TVP3020-135 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | Video Interface PALETTE(視頻接口調(diào)色器) |
| 中文描述： | 視頻接口盒（視頻接口調(diào)色器） |
| 文件頁數(shù)： | 20/98頁 |
| 文件大?。?/td> | 582K |
| 代理商： | TVP3020-135 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁當前第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁
2–6
Table 2–4. Input-Clock-Selection Register
INPUT-CLOCK-SELECT REGISTER (HEX) (see Note 1)
FUNCTION (see Note 2)
00
Select CLK0 as clock source
01
Select CLK1 as clock source
02
Select CLK2 as TTL clock source
03
04
Select CLK2 as TTL clock source
Select CLK2 and CLK2 as ECL clock source
10
Select CLK0 as doubled clock source
11
Select CLK1 as doubled clock source
12
Select CLK2 as TTL doubled clock source
13
Select CLK2 as TTL doubled clock source
14
Select CLK2/CLK2 as ECL doubled clock source
CLK0 is chosen at RESET as required for VGA pass-through.
NOTES:
1. Register bits 3 and 7 are don’t-care bits.
2. Register bits 5 and 6 are reserved.
3. When the clocks are selected from one input clock source to another, a minimum of 30 ns is needed
before the new clocks are stabilized and running.
The output-clock-selection register is used to program the desired divided-down frequencies for the
reference/shift and video clocks.
Table 2–5. Output-Clock-Selection Register Format
OUTPUT-CLOCK-SELECTION-REGISTER BITS (see Note 4)
FUNCTION (see Notes 4 5 6 and 7)
FUNCTION (see Notes 4, 5, 6, and 7)
5
0
0
0
0
1
1
4
0
0
1
1
0
0
3
0
1
0
1
0
1
2
x
x
x
x
x
x
1
x
x
x
x
x
x
0
x
x
x
x
x
x
VCLK/1 output ratio
VCLK/2 output ratio
VCLK/4 output ration
VCLK/8 output ratio
VCLK/16 output ratio
VCLK/32 output ratio
1
1
0
x
x
x
VCLK/64 output ratio
VCLK output held at logic 1
1
1
1
x
x
x
x
x
x
0
0
0
RCLK/1 output ratio (see Notes 4 and 7)
x
x
x
0
0
1
RCLK/2 output ratio (see Notes 4 and 7)
x
x
x
0
1
0
RCLK/4 output ratio (see Notes 4 and 7)
x
x
x
0
1
1
RCLK/8 output ratio (see Notes 4 and 7)
x
x
x
1
0
0
RCLK/16 output ratio (see Notes 4 and 7)
x
x
x
1
0
1
RCLK/32 output ratio (see Notes 4 and 7)
x
x
x
1
1
0
RCLK/64 output ratio (see Notes 4 and 7)
These lines indicate the RESET conditions as required for VGA pass-through mode.
NOTES:
4. Register bit 6 enables (logic 1) and disables (default – logic 0) the SCLK output buffer. Register bit
7 is a don’t-care bit.
5. When the clocks are selected from one mode to the other, a minimum of 30 ns is needed before
the new clocks are stabilized and running.
6. When the output-clock-selection register is written with 3F (hex), the clock counter is reset,
RCLK = SCLK = logic 0, and VCLK = logic 1.
7. SCLK is the same as RCLK except that it is disabled during blank. When the RCLK divide ratio is
chosen, this sets the SCLK ratio as well.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| TVP3025-135 | Video Interface PALETTE(三PLL，視頻接口調(diào)色器) |
| TVP3025-175 | Video Interface PALETTE(三PLL，視頻接口調(diào)色器) |
| TVP3030-175 | Video Interface PALETTE Exract(1600×1200，24位真彩色視頻接口調(diào)色器) |
| TVP3030-220 | Video Interface PALETTE Exract(1600×1200，24位真彩色視頻接口調(diào)色器) |
| TVP3030-250 | Video Interface PALETTE Exract(1600×1200，24位真彩色視頻接口調(diào)色器) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TVP3020-135MDN | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Texas Instruments 功能描述: |
| TVP3020-135PCE | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Texas Instruments 功能描述: |
| TVP3020-175MDN | 制造商:TI 制造商全稱:Texas Instruments 功能描述:Video Interface Palette |
| TVP3020-175PCE | 制造商:TI 制造商全稱:Texas Instruments 功能描述:Video Interface Palette |
| TVP3020-200MDN | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。