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參數(shù)資料
| 型號： | TVP3020-135 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | Video Interface PALETTE(視頻接口調(diào)色器) |
| 中文描述： | 視頻接口盒（視頻接口調(diào)色器） |
| 文件頁數(shù)： | 66/98頁 |
| 文件大?。?/td> | 582K |
| 代理商： | TVP3020-135 |
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3–4
3.5 Timing Requirements (see Note 5)
TVP3020
-135
MIN
TVP3020
-175
MIN
TVP3020
-200
MIN
UNIT
MAX
135
MAX
170
MAX
200
DOTCLK frequency
CLK0 frequency for VGA pass-through mode
(see Note 6)
MHz
85
85
85
MHz
tcyc
Clock cycle time
TTL
ECL
7.4
7.4
10
10
35
7.1
5.8
10
10
35
7.1
5.0
10
10
35
ns
tsu1
th1
tsu2
th2
Setup time, RS(0 – 3) valid before RD or WR
↓
Hold time, RS(0 – 3) valid after RD or WR
↓
Setup time, D(0 – 7)valid before WR
↑
Hold time, D(0 – 7)valid after WR
↑
Setup time, VGA(0 – 7) and VGAHS, VGAVS, and
VGABL valid before CLK0
↑
(see Note 7)
Hold time, VGA(0 – 7) and VGAHS, VGAVS, and
VGABL valid after CLK0
↑
(see Note 7)
Setup time, P(0 – 63) and PSEL valid before LCLK
↑
(see Note 8)
Hold time, P(0 – 63) and PSEL valid after LCLK
↑
(see Note 8)
Setup time, SYSHS, SYSVS, and SYSBL valid
before VCLK
↓
Hold time, SYSHS, SYSVS, and SYSBL valid after
VCLK
↓
Pulse duration, RD or WR low
Pulse duration, RD or WR high
ns
ns
ns
ns
0
0
0
tsu3
2
2
2
ns
th3
2
2
2
ns
tsu4
2
2
2
ns
th4
5
5
5
ns
tsu5
5
5
5
ns
th5
1
1
1
ns
tw1
tw2
50
30
3
3
3
3
30
15
50
30
3
2.5
50
30
3
2
3
2
30
15
ns
ns
tw3
Pulse duration clock high
Pulse duration, clock high
TTL
ECL
TTL
ECL
ns
tw4
Pulse duration clock low
Pulse duration, clock low
3
ns
2.5
30
15
tw5
tw6
NOTES:
Pulse duration, SFLAG high (see Note 9)
Pulse duration, SCLK high (see Note 9)
5. TTL input signals are 0 to 3 V with less than 3 ns rise/fall time between the 10% and 90% levels unless
otherwise specified. ECL input signals are VDD–1.8 V to VDD–0.8 V with less than 2 ns rise/fall time
between the 20% and 80% levels. For input and output signals, timing reference points are at the 10% and
90% signal levels. Analog output loads are less than 10 pF. D<0:7> output loads are less than 50 pF. All
other output loads are less than 50 pF unless otherwise specified.
6. In VGA mode, CLK0 minimum pulse duration for clock low should be greater than 4.8 ns. If VGA switching
is to be performed using self-clocked timing, the maximum pixel rate cannot exceed 50 MHz.
7. Reference to CLK0 input only.
8. RCLK is delayed from SCLK in such a way that when RCLK is connected to LCLK, the timing is essentially
the same as the TLC3407x family of parts.
9. This parameter applies when the split shift register transfer (SSRT) function is enabled. See Section 2.15
for details.
ns
ns
55
55
55
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TVP3020-135MDN | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Texas Instruments 功能描述: |
| TVP3020-135PCE | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Texas Instruments 功能描述: |
| TVP3020-175MDN | 制造商:TI 制造商全稱:Texas Instruments 功能描述:Video Interface Palette |
| TVP3020-175PCE | 制造商:TI 制造商全稱:Texas Instruments 功能描述:Video Interface Palette |
| TVP3020-200MDN | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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