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參數(shù)資料
| 型號： | TVP3020-135 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | Video Interface PALETTE(視頻接口調(diào)色器) |
| 中文描述： | 視頻接口盒（視頻接口調(diào)色器） |
| 文件頁數(shù)： | 17/98頁 |
| 文件大小： | 582K |
| 代理商： | TVP3020-135 |
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2–3
Table 2–2. Indirect Register Map (Extended Registers) (Continued)
INDEX REGISTER
(HEX)
R/W
DEFAULT
(HEX)
REGISTER ADDRESSED
BY INDEX REGISTER
36
R/W
XX
Color-Key Blue Low
37
R/W
XX
Color-Key Blue High
38
R/W
10
Color-Key Control Register
39
Reserved-Undefined
3A
R/W
00
Sense Test Register
3B
R
XX
Test Data Register
3C
R
XX
CRC LSB
3D
R
XX
CRC MSB
3E
W
XX
CRC Control Register
3F
R
20
ID Register
FF
W
XX
Reset Register
NOTE: Reserved registers should be avoided; otherwise, circuit behavior could deviate
from that specified. Reserved-undefined registers are nonexistent locations on
the register map.
2.2
The color palette is addressed by an internal 8-bit address register for reading/writing data from/to the RAM.
This register is automatically incremented following a RAM transfer, allowing the entire palette to be
read/written with only one access of the address register. When the address register increments beyond
the last location in RAM, it is reset to the first location (address 0). All read and write accesses to the RAM
are asynchronous to SCLK, VCLK, and dot clock but performed within one dot clock. Therefore, they do not
cause any noticeable disturbance on the display.
Color Palette
The color RAM is 24 bits wide for each location and 8 bits wide for each color. Since the MPU access is eight
bits wide, the color data stored in the palette is eight bits even when the six-bit mode is chosen (8/6 = 0).
If the six-bit mode is chosen, the two MSBs of color data in the palette have the values previously written.
However, if they are read back in the six-bit mode, the two MSBs are 0s to be compatible with IMSG176 and
Bt176. The output multiplexer shifts the six LSB bits to the six MSB positions and fills the two LSBs with 0s
after the color palette. The multiplexer then feeds the data to the DAC. The test register and the CRC
calculation both take data after the output multiplexer, enabling total system verification. The color palette
access is described in the following two sections, and it is fully compatible with IMSG176/8 and Bt476/8.
2.2.1
To load the color palette, the MPU must first write to the address register (write mode) with the address where
the modification is to start. This is then followed by three successive writes to the palette holding register
with 8 bits of red, green, and blue data. After the blue write cycle, the three bytes of color data are
concatenated into a 24-bit word that is then written to the RAM location specified by the address register.
The address register then increments to the next location, which the MPU may modify by simply writing
another sequence of red, green, and blue data. A block of color values in consecutive locations may be
written to by writing the start address and performing continuous red, green, and blue write cycles until the
entire block has been written.
Writing to Color-Palette RAM
2.2.2
Reading from the palette is performed by writing to the address register (read mode) with the location to be
read. This then initiates a transfer from the palette RAM into the holding register, followed by an increment
of the address register. Three successive MPU reads from the holding register produce red, green, and blue
color data (6 or 8 bits depending on the 8/6 mode) for the specified location. Following the blue read cycle,
Reading From Color-Palette RAM
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TVP3020-135MDN | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Texas Instruments 功能描述: |
| TVP3020-135PCE | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Texas Instruments 功能描述: |
| TVP3020-175MDN | 制造商:TI 制造商全稱:Texas Instruments 功能描述:Video Interface Palette |
| TVP3020-175PCE | 制造商:TI 制造商全稱:Texas Instruments 功能描述:Video Interface Palette |
| TVP3020-200MDN | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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