參數(shù)資料
型號(hào)： TVP3020-135
廠商： Texas Instruments, Inc.
英文描述： Video Interface PALETTE(視頻接口調(diào)色器)
中文描述： 視頻接口盒（視頻接口調(diào)色器）
文件頁數(shù)： 29/98頁
文件大?。?/td> 582K
代理商： TVP3020-135
2–15
2.4.6
Multiplex-Control Registers
The pixel port multiplexer is controlled by two 8-bit registers in the indirect register map (see Section 2.1).
The various multiplexing modes can be selected according to the following table.
Table 2–6. Multiplex Mode and Bus-Width Selection
MODE
SUB-
MODE
MULTIPLEX-
CONTROL
REGISTER 1
(HEX)
MULTIPLEX-
CONTROL
REGISTER 2
(HEX)
DATA
BITS
PER
PIXEL
(see
Note 8)
PIXEL
BUS
WIDTH
MULTI-
PLEX
RATIO
(see
Note 9)
OVERLAY
BITS
PER
PIXEL
TABLE
REFERENCE
(see
Note 10)
VGA
80
98
8
8
1
NA
v1
Pseud
Color
d
1
80
00
1
4
4
NA
s1
80
01
1
8
8
NA
s2
80
02
1
16
16
NA
s3
80
03
1
32
32
NA
s4
80
04
1
64
64
NA
s5
2
80
08
2
4
2
NA
s6
80
09
2
8
4
NA
s7
80
0A
2
16
8
NA
s8
80
0B
2
32
16
NA
s9
80
0C
2
64
32
NA
s10
3
80
10
4
4
1
NA
s11
80
11
4
8
2
NA
s12
80
12
4
16
4
NA
s13
80
13
4
32
8
NA
s14
80
14
4
64
16
NA
s15
4
80
19
8
8
1
NA
s16
80
1A
8
16
2
NA
s17
80
1B
8
32
4
NA
s18
80
1C
8
64
8
NA
s19
NOTES:
8. Data bits per pixel is the number of bits of pixel port information used as color data for each displayed pixel,
often referred to as the number of bit planes.
9. Multiplex ratio indicates the number of pixels per bus load or the number of pixels associated with each
LCLK (load clock) pulse. For example, with a 32-bit pixel bus width and 8 bit planes, each bus load consists
of four pixels. In a typical implementation, the LCLK signal is either connected to or derived from RCLK.
Therefore, the RCLK divide ratio must be chosen as a function of the multiplex mode selected. The RCLK
divide ratio is not automatically set by mode selection but must be programmed in the output clock selection
register by the user.
10. This column is a reference to Tables 2–7 through 2–11, where the actual manipulation of pixel information
and pixel latching sequences are illustrated for each of the multiplexing modes.
11. It is recommended that all unused input terminals be connected to ground to conserve power.
12. Multiplex-control register 2 bit 7 enables (logic 1) and disables (logic 0 ) the VGA port. If auxiliary-window
or port-select switching is to be done involving the VGA port, this bit needs to be set to a logic 1 as well as
programming for the correct direct-color mode. For example, if auxiliary windowing is to be done with
direct-color submode 1 (32-bit pixel bus) and VGA, instead of programming 1B (hex), multiplex-control
register 2 should be programmed to 9B (hex). If only VGA pass-through is desired, the values should be
programmed for VGA mode as indicated in Table 2–6. If only VGA pass-through is desired, the values
should be programmed as indicated in Table 2–6 for VGA mode.
相關(guān)PDF資料
PDF描述
TVP3025-135 Video Interface PALETTE(三PLL，視頻接口調(diào)色器)
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TVP3030-175 Video Interface PALETTE Exract(1600×1200，24位真彩色視頻接口調(diào)色器)
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
TVP3020-135MDN 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Texas Instruments 功能描述:
TVP3020-135PCE 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Texas Instruments 功能描述:
TVP3020-175MDN 制造商:TI 制造商全稱:Texas Instruments 功能描述:Video Interface Palette
TVP3020-175PCE 制造商:TI 制造商全稱:Texas Instruments 功能描述:Video Interface Palette
TVP3020-200MDN 制造商:Rochester Electronics LLC 功能描述:- Bulk
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