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參數(shù)資料
| 型號： | TVP3020-135 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | Video Interface PALETTE(視頻接口調(diào)色器) |
| 中文描述： | 視頻接口盒（視頻接口調(diào)色器） |
| 文件頁數(shù)： | 48/98頁 |
| 文件大?。?/td> | 582K |
| 代理商： | TVP3020-135 |
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2–34
2.12 Frame-Buffer Interface
The TVP3020 provides three output clock signals and one input clock signal for controlling the frame-buffer
interface: SCLK, RCLK, LCLK, and VCLK. SCLK can be used to clock out data from VRAM shift registers
directly. Split-shift register-transfer function is also supported. RCLK is provided so that pixel port (P0–P63)
data loading can be synchronized to the VRAM. LCLK rising edges latch data presented on the pixel port,
and VCLK is used to clock and synchronize the video control signals such as SYSHS, SYSVS, SYSBL.
Clocking of the frame-buffer interface (self-clocked and externally-clocked timing) is discussed in detail in
Section 2.3.2.
The 64-terminal interface allows many operational display modes as defined in Section 2.4 and Table 2–6.
The pixel latching sequence is initiated by a rising edge on LCLK. For those multiplexed modes in which
multiple pixels are latched on one LCLK rising edge, the pixel clock shifts the pixels out starting with the
pixels that reside on the low numbered pixel port terminals. For example, in an 8-bit-per-pixel pseudo-color
mode with an 8:1 multiplex ratio, the pixel display sequence is P(0–7), P(8–15), P(16–23), P(24–31),
P(32–39), P(40–47), P(48–55), and P(56–63).
The Viewpoint frame-buffer interface also supports little- and big-endian data formats on the pixel bus. This
can be controlled by general-control register bit 3. See Sections 2.4.1 and 2.16.1, and Appendix C for details
of operation.
2.13 Analog Output Specifications
The DAC outputs are controlled by three current sources (only two for IOR and IOB) as shown in
Figure 2–13. The default condition is to have 0 IRE difference between blank and black levels, which is
shown in Figure 2–15. If a 7.5-IRE pedestal is desired, it can be selected by setting bit 4 of the general-control
register. This video output is shown in Figure 2–14.
SYNC
(IOG Only)
BLANK
G0 – G7
≈
15 pF
RL
AVDD
IOG
C
(Stray+Load)
Figure 2–13. Equivalent Circuit of the Current Output (IOG)
A resistor (R
SET
) is needed between the FS ADJ terminal and GND to control the magnitude of the full-scale
video signal. The IRE relationships in Figures 2–14 and 2–15 are maintained regardless of the full-scale
output current.
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PDF描述 |
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| TVP3025-135 | Video Interface PALETTE(三PLL，視頻接口調(diào)色器) |
| TVP3025-175 | Video Interface PALETTE(三PLL，視頻接口調(diào)色器) |
| TVP3030-175 | Video Interface PALETTE Exract(1600×1200，24位真彩色視頻接口調(diào)色器) |
| TVP3030-220 | Video Interface PALETTE Exract(1600×1200，24位真彩色視頻接口調(diào)色器) |
| TVP3030-250 | Video Interface PALETTE Exract(1600×1200，24位真彩色視頻接口調(diào)色器) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TVP3020-135MDN | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Texas Instruments 功能描述: |
| TVP3020-135PCE | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Texas Instruments 功能描述: |
| TVP3020-175MDN | 制造商:TI 制造商全稱:Texas Instruments 功能描述:Video Interface Palette |
| TVP3020-175PCE | 制造商:TI 制造商全稱:Texas Instruments 功能描述:Video Interface Palette |
| TVP3020-200MDN | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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