2–37
If the SSRT function is enabled but SFLAG is held low, the SCLK runs as if the SSRT function is disabled.
Since the SFLAG input is not qualified by the BLANK signal within the palette, it needs to be held low or
disabled any time the SSRT SCLK pulse is not intended. Refer to Section 2.3 and Figures 2–2 through 2–5
for more system details.
2.16 Control-Register Definitions
2.16.1
General-Control Register
The general-control register is used to control various functions of the Viewpoint palette. It can be accessed
by the MPU at any time. Bit 7 of the general-control register corresponds to data bus bit 7, index = 1D (hex).
Table 2–12. General-Control Register
BIT
NAME
VALUES
DESCRIPTION
GCR7
0: External OVS terminal
(default)
Overscan-control select. Selects external terminal control or internally
generated overscan control See Section 2 7
generated overscan control. See Section 2.7.
1: Internal
GCR6
0: Disable (default)
Overscan enable. Specifies whether to enable the user-defined overscan
Overscan enable. Specifies whether to enable the user defined overscan
screen borders.
1: Enable
GCR5
0: Disable
Sync enable. This bit specifies whether SYNC information is to be output onto
IOG.
1: Enable (default)
GCR4
0: 0 IRE (default)
Pedestal control. This bit specifies whether a 0 or 7.5 IRE blanking pedestal
istobegeneratedonthevideooutputs 0IREspecifiesthattheblackandblank
isto be generated on the video outputs. 0 IRE specifies that the black and blank
levels are the same.
1: 7.5 IRE
GCR3
0: Little endian (default)
Little-endian/big-endian select. Selects either little- or big-endian format for the
Little endian/big endian select. Selects either little or big endian format for the
pixel-bus frame-buffer interface. See Sections 2.4 and Appendix C.
1: Big-Endian
GCR2
0: Disable (default)
Split shift-register-transfer enable See Section 2 15
Split shift-register-transfer enable. See Section 2.15.
1: Enable
GCR1
0: Active (low) (default)
VSYNCOUT output polarity See Section 2 14
VSYNCOUT output polarity. See Section 2.14.
1: Active (high)
GCR0
0: Active (low) (default)
HSYNCOUT output polarity See Section 2 14
HSYNCOUT output polarity. See Section 2.14.
1: Active (high)