![](http://datasheet.mmic.net.cn/220000/VPX3214_datasheet_15512234/VPX3214_34.png)
PRELIMINARY DATA SHEET
VPX 3220 A, VPX 3216 B, VPX 3214 C
MICRONAS INTERMETALL
34
I
2
C-Register Table
Name
Function
Mode
Number
of Bits
I
2
C Reg.
Address
Output Multiplexer
F2
8
w
Output Enable
OENA
direct
bit [0] :
1
0
Enable Video Port A
Disable / High Impedance Mode
aen
direct
bit [1] :
1
0
Enable Video Port B
Disable / High Impedance Mode
ben
direct
bit [2] : reserved (must be set to zero)
direct
bit [3] :
1
0
Enable Controls (HREF, VREF, PREF, HF#, FE#, ALPHA)
Disable / High Impedance Mode
zen
direct
bit [4] :
1
Enable LLC-Clock to HF-Pad
(if transport rate is 13 MHz and internal clock source is used)
llcen
direct
bit [5] :
1
Enable FSY-Data to HF-Pad
(if transport rate is 20 MHz and internal clock source is used)
fsyen
direct
bit [6] :
1
Synchronize HREF, VREF with PIXCLK
hvsynbyq
direct
bit [7] :
1
disable OEQ pin function
F8
6 / 8
w
Pad Driver Strength – TTL Output Pads Typ A
DRIVER_A
bit [2:0] :
Driver strength of Port A[7:0]
stra1
bit [5:3] :
Driver strength of PIXCLK, HF# and FE#
stra2
bit [7:6] :
additional PIXCLK driver strength
strength = bit [5:3] | {bit [7:6], 0}
F9
6 / 8
w
Pad Driver Strength – TTL Output Pads Typ B
DRIVER_B
bit [2:0] :
Driver strength of Port B[7:0] and C[7:0]
strb1
bit [5:3] :
Driver strength of HREF, VREF, PREF and ALPHA
strb2
bit [7:6] :
reserved (must be set to zero)
The control register modes are
– w: write/read register
– d: register is double latched
– A: register is available only in VPX 3220 A; VPX 3216 B returns valid ACK, although no internal action is performed
– r:
read-only register
The mnemonics used in the Intermetall VPX demo software are given in the last column.