參數(shù)資料
型號(hào): VPX3214
廠商: Electronic Theatre Controls, Inc.
英文描述: Video Pixel Decoders
中文描述: 視頻解碼器像素
文件頁數(shù): 43/80頁
文件大?。?/td> 752K
代理商: VPX3214
VPX 3220 A, VPX 3216 B, VPX 3214 C
PRELIMINARY DATA SHEET
MICRONAS INTERMETALL
43
5. JTAG Boundary-Scan, Test Access Port (TAP)
The design of the Test Access Port, which is used for
Boundary-Scan Test conforms to standard IEEE
1149.1-1990, with one exception. Also included is a list
of the mandatory instructions supported, as well as the
optional instructions. This is only a brief overview of
some of the basics, as well as any optional features
which are incorporated. The IEEE 1149.1 document
may be necessary for a more concise description. Final-
ly, an adherence section goes through a checklist of top-
ics and describes how the design conforms to the stan-
dard.
The implementation of the instructions HIGHZ and
CLAMP conforms to the supplement P1149.1/D11 (Oc-
tober 1992) to the standard 1149.1-1990.
5.1. General Description
The TAP in the VPX is incorporated using the four signal
interface. The interface includes TCK, TMS, TDI, and
TDO. The optional TRESET signal is not used. This is
not needed because the chip has an internal power-on-
reset which will automatically steer the chip into the
TEST-LOGIC-RESET state. The goal of the interface is
to provide a means to test the boundary of the chip.
There is no support for internal or BIST(built-in self test).
The one exception to IEEE 1149.1 is that the TDO output
is shared with the ALPHA signal. This was done be-
cause of I/O restrictions on the chip (see section 5.3.
“Exceptions to IEEE 1149.1” for more information).
5.2. TAP Architecture
The TAP function consists of the following blocks: TAP-
controller, instruction register, boundary-scan register,
bypass register, optional device identification register,
and master mode register.
5.2.1. TAP Controller
The TAP Controller is responsible for responding to the
TCK and TMS signals. It controls the transition between
states of this machine. These states control selection of
the data or instruction registers and the actions which
occur in these registers. These include capture, shifting,
and update. See Fig. 5–1 of IEEE 1149.1 for TAP state
diagram.
5.2.2. Instruction Register
The instruction register chooses which one of the data
registers is placed between the TDI and TDO pins when
the select data register state is entered in the TAP con-
troller. When the select instruction register state is ac-
tive, the instruction register is placed between the TDI
and TDO.
Instructions
The following instructions are incorporated:
– bypass
– sample/preload
– extest
– master mode
– ID code
– HIGHZ
– CLAMP
5.2.3. Boundary Scan Register
The boundary-scan register (BSR) consists of bound-
ary-scan cells (BSCs) which are distributed throughout
the chip. These cells are located at or near the I/O pad.
It allows sampling of inputs, controlling of outputs, and
shifting between each cell in a serial fashion to form the
BSR. This register is used to verify board interconnect.
Input Cell
The input cell is constructed to achieve capture only.
This is the minimal cell necessary since Internal Test
(INTEST) is not supported. The cell captures either the
system input in the CAPTURE-DR State or the previous
cells output in the SHIFT-DR State. The captured data
is then available to the next cell. No action is taken in the
UPDATE-DR State. See Figure 10–11 of IEEE 1149.1
for reference.
Output Cell
The output cell will allow both capture and update. The
capture flop will obtain system information in the CAP-
TURE-DR State or previous cells information in the
SHIFT-DR state. The captured data is available to the
next cell. The captured or shifted data is downloaded to
the update flop during the UPDATE-DR state. The data
from the update flop is then multiplexed to the system
output pin when the EXTEST instruction is active. Other-
wise, the normal system path exists where the signal
from the system logic flows to the system output pin. See
Fig. 10–12 of IEEE 1149.1 for reference.
相關(guān)PDF資料
PDF描述
VPX3214C Video Pixel Decoders
VPX3224D Video Pixel Decoders
VPX3224E Video Pixel Decoders
VPX322XE Video Pixel Decoders
VQ1000J N-Channel Enhancement-Mode MOSFET Transistor(最小漏源擊穿電壓60V,夾斷電流0.225A的N溝道增強(qiáng)型MOSFET晶體管)
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
VPX3214C 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Video Pixel Decoders
VPX3214C(PLCC44) 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Color Decoder Circuit
VPX3214C(QFP44) 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Color Decoder Circuit
VPX3216B 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Video Pixel Decoders
VPX3216B(PLCC44) 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Color Decoder Circuit