- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄359412 > VPX3214 (Electronic Theatre Controls, Inc.) Video Pixel Decoders PDF資料下載
參數(shù)資料
| 型號： | VPX3214 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Video Pixel Decoders |
| 中文描述： | 視頻解碼器像素 |
| 文件頁數(shù)： | 35/80頁 |
| 文件大小： | 752K |
| 代理商： | VPX3214 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁當前第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁
PRELIMINARY DATA SHEET
VPX 3220 A, VPX 216 B, VPX 3214 C
MICRONAS INTERMETALL
35
4.8. FP Control and Status Registers
The tables below list the registers which are currently
defined. Electrically, all of the registers in the FP subad-
dress space are both readable and writeable. Function-
ally, they are intended for either read or write (as shown
in the ‘mode’ column)
Warning:
The FP subaddress space accesses the RAM
of the fast processor. It is therefore very sensitive to
unintended access. In particular, the user must be sure
not to overwrite reserved areas.
FP-Register Table
FP Reg.
Address
Number
of Bits
Mode
Function
Name
Load Table for Window #1
WinLoadTab1
88
12
w
Vertical Begin
bit [8:0] :
Vertical Begin (field line number)
minimum line number
maximum line number
7
determined by current TV line standard
vbeg1
A
bit [11:9]
sharpness control .... regulates the subjective sharpness
by selecting filters to admitting horizontal alias / blurring
maximum blurring
.....
more blurring
default filter setting
more aliasing
.....
maximum aliasing
1 1 1
1 1 0
1 0 1
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
set filters for pass-thru
89
12
w
Vertical Lines In
bit [8:0] :
Number of input lines
vlinei1
bit [9]
reserved (must be set to zero)
bit [11:10] :
field flag
Window disabled
Window enabled in ODD fields only
Window enabled in EVEN fields only
Window enabled in both fields
1 1
1 0
0 1
0 0
8A
12
w
Vertical Lines Out
bit [8:0] :
Number of output lines
vlineo1
bit [11:9]
reserved (must be set to zero)
8B
12
w
Horizontal Begin
bit [10:0] :
Horizontal start of window
hbeg1
bit [11]
reserved (must be set to zero)
8C
12
w
Horizontal Length
bit [10:0] :
Horizontal length of window
hlen1
bit [11]
reserved (must be set to zero)
8D
12
w
Number of Pixels
bit [10:0] :
Number of active pixels per line
npix1
bit [11]
reserved (must be set to zero)
The control register modes are
– w: write/read register
– r:
read-only register
– A: register or register field has function only in VPX 3220 A
The mnemonics used in the Intermetall VPX demo software are given in the last column.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| VPX3214C | Video Pixel Decoders |
| VPX3224D | Video Pixel Decoders |
| VPX3224E | Video Pixel Decoders |
| VPX322XE | Video Pixel Decoders |
| VQ1000J | N-Channel Enhancement-Mode MOSFET Transistor(最小漏源擊穿電壓60V,夾斷電流0.225A的N溝道增強型MOSFET晶體管) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| VPX3214C | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Video Pixel Decoders |
| VPX3214C(PLCC44) | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Color Decoder Circuit |
| VPX3214C(QFP44) | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Color Decoder Circuit |
| VPX3216B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Video Pixel Decoders |
| VPX3216B(PLCC44) | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Color Decoder Circuit |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。