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參數(shù)資料
| 型號： | VPX3214 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Video Pixel Decoders |
| 中文描述： | 視頻解碼器像素 |
| 文件頁數(shù)： | 77/80頁 |
| 文件大?。?/td> | 752K |
| 代理商： | VPX3214 |
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VPX 3220 A, VPX 3216 B, VPX 3214 C
PRELIMINARY DATA SHEET
MICRONAS INTERMETALL
77
Video Pixel Decoder Family Addendum
1. Introduction for Addendum
VPX 3214C has two additional features compared to the
VPX 3220A and VPX 3216B:
– another output timing mode called NewVACT and
– low power mode.
2. New Output Timing – NewVACT
The VPX family operates with a system and sampling
clock of 20.25 MHz. When the oscillator is not locked to
the line frequency of the processed video signal, the
number of samples per video scan line can vary from line
to line. The HREF signal marks the active video line and
has a fixed width of 1056 clocks. The inactive part of the
HREF can therefore vary in length. The same principle
applies to the VACT signal, the difference being that the
active length of VACT equals the number of output pixels
times transport rate of either 20.25 or 13.5 MHz. This be-
havior of HREF and VACT signals is well suited for the
systems using state machines to handle these signals
and data delivered from VPX. On the other hand this be-
havior causes problems in case the system uses plain
counters to decide when to strobe the data. These sys-
tems require that the inactive period of HREF also has
a fixed length: they use the inactive going edge of HREF
to reset their counters, count afterwards a certain
amount of clocks and then strobe the preprogrammed
number of data almost regardless of the state of VACT
signal. That’s why this new timing mode was introduced.
In this mode signal at VACT pin has an unpredictable be-
havior and NewVACT signal is available at the HREF pin
carrying all the information. It goes inactive, stays inac-
tive for the programmable number of transport rate
clocks. This inactive phase is at least 8 clocks long and
can be extended in clock units to the maximum length of
23 by writing the field [3:0] of the OFIFO register (I
2
C ad-
dress 0xF0). After that NewVACT goes active exactly
before the first valid video data, so it still can be used as
qualifier for the start of data. It stays active for the rest
of the line regardless of the number of valid video data,
so it can not be used as the end-qualifier. The system us-
ing the data has to count properly and strobe only the
valid data.
After reset, the VPX operates in its usual output timing
mode. There are two registers controlling the new mode.
The FP register is used to switch it on and off and I
2
C
register is used to control the length of the HREF inactive
period.
Symbol
Parameter
Min.
Typ.
Max.
Unit
Test Conditions
t
HNVL
Hold Time of inactive going NewVACT after
PIXCLK
20
ns
t
HNVH
Hold Time of active going NewVACT after
PIXCLK
15
ns
t
HV
Hold Time of VREF change after PIXCLK
10
ns
NewVACT–Timing (13.5/20.25MHz)
PIXCLK
HREF
VREF
DATA
oddfield changes
evenfield changes
1. data
2. data
......
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| VPX3214C | Video Pixel Decoders |
| VPX3224D | Video Pixel Decoders |
| VPX3224E | Video Pixel Decoders |
| VPX322XE | Video Pixel Decoders |
| VQ1000J | N-Channel Enhancement-Mode MOSFET Transistor(最小漏源擊穿電壓60V,夾斷電流0.225A的N溝道增強(qiáng)型MOSFET晶體管) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| VPX3214C | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Video Pixel Decoders |
| VPX3214C(PLCC44) | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Color Decoder Circuit |
| VPX3214C(QFP44) | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Color Decoder Circuit |
| VPX3216B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Video Pixel Decoders |
| VPX3216B(PLCC44) | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Color Decoder Circuit |
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