參數(shù)資料
型號(hào)： VPX322XE
廠商： MICRONAS SEMICONDUCTOR HOLDING AG
英文描述： Video Pixel Decoders
中文描述： 視頻解碼器像素
文件頁(yè)數(shù)： 14/92頁(yè)
文件大小： 567K
代理商： VPX322XE
ADVANCE INFORMATION
VPX 322xE
14
Micronas
2.3.9. Luminance Notch
If a composite video signal is applied, the color informa-
tion is suppressed by a programmable notch filter. The
position of the filter center frequency depends on the
subcarrier frequency for PAL/NTSC. For SECAM, the
notch is directly controlled by the chroma carrier fre-
quency. This considerably reduces the cross-lumi-
nance. The frequency responses for all three systems
are shown in Fig. 2
–
11. In S-VHS mode, this filter is by-
passed.
2.4. Video Sync Processing
Fig. 2
–
10 shows a block diagram of the front-end sync
processing. To extract the sync information from the
video signal, a linear phase lowpass filter eliminates all
noise and video contents above 1 MHz. The sync is sep-
arated by a slicer; the sync phase is measured. The in-
ternal controller can select variable windows to improve
the noise immunity of the slicer. The phase comparator
measures the falling edge of sync, as well as the inte-
grated sync pulse.
The sync phase error is filtered by a phase-locked loop
that is computed by the FP. All timing in the front-end is
derived from a counter that is part of this PLL, and it thus
counts synchronously to the video signal.
A separate hardware block measures the signal back
porch and also allows gathering the maximum/minimum
of the video signal. This information is processed by the
FP and used for gain control and clamping.
For vertical sync separation, the sliced video signal is in-
tegrated. The FP uses the integrator value to derive ver-
tical sync and field information.
Frequency and phase characteristics of the analog vid-
eo signal are derived from PLL1. The results are fed to
dB
MHz
10
0
2
4
6
8
10
0
–
10
–
20
–
30
–
40
dB
MHz
10
0
2
4
6
8
10
0
–
10
–
20
–
30
–
40
PAL/NTSC notch filter
Fig. 2
–
11:
Frequency responses of the luma
notch filter for PAL, NTSC, SECAM
SECAM notch filter
the rest of the video processing system in the backend.
The resizer unit uses them for data interpolation and
orthogonalization. A separate timing block derives the
timing reference signals HREF and VREF from the hori-
zontal sync.
Fig. 2
–
10:
Sync separation block diagram
lowpass
1 MHz &
sync
slicer
horizontal
sync
separation
clamp &
signal
measurement
phase
comparator
& lowpass
counter
front-end
timing
front
sync
generator
clock
synthesizer
syncs
front sync
skew
vblank
field
clock
H/V syncs
clamping
video
input
color key
FIFO_write
PLL1
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