參數(shù)資料
型號： VPX322XE
廠商： MICRONAS SEMICONDUCTOR HOLDING AG
英文描述： Video Pixel Decoders
中文描述： 視頻解碼器像素
文件頁數(shù)： 23/92頁
文件大小： 567K
代理商： VPX322XE
ADVANCE INFORMATION
VPX 322xE
23
Micronas
2.8.3. Half Clock Mode
For applications demanding a low bandwidth for the
transmission between video decoder and graphics con-
troller, the clock signal qualifying the output pixels
(PIXCLK) can be divided by 2. This mode is enabled by
setting bit[5] of the FP-RAM 0x150 [halfclk]. Note that
the output format ITU-R601 must be selected. The tim-
ing of the data and clock signals in this case is described
in Figure 2
–
26.
If the half-clock mode is enabled, each second pulse of
PIXCLK is gated. PIXCLK can be used as a qualifier for
valid data. To ensure that the video data stream can be
spread, the selected number of valid output samples
should not exceed 400.
Chrominance
(Port B)
VACT
LLC
C
1
C
n
–
1
C
n
Luminance
(Port A)
Y
1
Y
n
–
1
Y
n
PIXCLK
Fig. 2
–
24:
Output timing in single clock mode
Video
(Port A)
VACT
LLC
C
1
C
n
–
1
C
n
PIXCLK
Y
1
Y
n
–
1
Y
n
Fig. 2
–
25:
Output timing in double clock mode
Chrominance
(Port B)
VACT
LLC
Luminance
(Port A)
Y
1
Y
n
PIXCLK
C
1
C
n
Fig. 2
–
26:
Output timing in half clock mode
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