參數(shù)資料
型號(hào)： VPX322XE
廠商： MICRONAS SEMICONDUCTOR HOLDING AG
英文描述： Video Pixel Decoders
中文描述： 視頻解碼器像素
文件頁數(shù)： 37/92頁
文件大小： 567K
代理商： VPX322XE
ADVANCE INFORMATION
VPX 322xE
37
Micronas
Write to Hardware Control Registers
S
1 0 0 0 0 1 1 0
ACK
sub-addr
ACK
send data-byte
ACK
P
Read from Hardware Control Registers
S
1 0 0 0 0 1 1 0
ACK
sub-addr
ACK
S
1 0 0 0 0 1 1 1
ACK
receive data-byte
NAK
P
Note:
S =
P =
ACK = Acknowledge-Bit (active low on SDA from receiving device)
NAK = No Acknowledge-Bit (inactive high on SDA from receiving device)
I
2
C-Bus Start Condition
I
2
C-Bus Stop Condition
Fig. 2
–
41:
I
2
C bus protocol
(MSB first)
SDA
SCL
1
0
S
P
2.15.5. FP Control and Status Registers
Due to the internal architecture of the VPX, the IC cannot
react immediately to all I
2
C requests which interact with
the embedded processor (FP). The maximum response
timing is appr. 20 ms (one TV field) for the FP processor
if TV standard switching is active. If the addressed pro-
cessor is not ready for further transmissions on the I
2
C
bus, the clock line SCL is pulled low. This puts the cur-
rent transmission into a wait state called clock synchro-
nization. After a certain period of time, the VPX releases
the clock and the interrupted transmission is carried on.
Before accessing the address or data registers for the
FP interface (FPRD, FPWR, FPDAT), make sure that
the busy bit of FP is cleared (FPSTA).
Write to FP
S
1 0 0 0 0 1 1 0
ACK
FPWR
ACK
send FP-address-
byte high
ACK
send FP-address-
byte low
ACK
P
S
1 0 0 0 0 1 1 0
ACK
FPDAT
ACK
send data-byte
high
ACK
send data-byte
low
ACK
P
Read from FP
S
1 0 0 0 0 1 1 0
ACK
FPRD
ACK
send FP-address-
byte high
ACK
send FP-address-
byte low
ACK
P
S
1 0 0 0 0 1 1 0
ACK
FPDAT
ACK
S
1 0 0 0 0 1 1 1
ACK
receive data-byte
high
ACK
receive data-byte
low
NAK
P
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