參數(shù)資料
型號(hào)： VPX322XE
廠商： MICRONAS SEMICONDUCTOR HOLDING AG
英文描述： Video Pixel Decoders
中文描述： 視頻解碼器像素
文件頁(yè)數(shù)： 22/92頁(yè)
文件大?。?/td> 567K
代理商： VPX322XE
ADVANCE INFORMATION
VPX 322xE
22
Micronas
Table 2
–
6:
Luminance control codes
Luma Value
Video Event
Video Event
Phase Information
01
VACT end
last pixel was the last active pixel
refers to the last pixel
02
VACT begin
next pixel is the first active pixel
refers to the next pixel
03
HREF active line
begin of an active video line
refers to the current pixel
04
HREF blank line
begin of a blank line
refers to the current pixel
05
VREF even
begin of an even field
refers to the current pixel
06
VREF odd
begin of an odd field
refers to the current pixel
Fig. 2
–
23:
Detailed data output with timing event codes (double clock mode)
C
rn
–
1
Y
n
C
r1
Y
2
C
bn
–
1
Y
n
–
1
C
b1
Y
1
FFh
02h
03h
FFh
FEh
01h
DATA
(Port A)
VACT
LLC
PIXCLK
HREF
2.8. Video Data Transfer
The VPX supports a synchronous video interface. Video
data arrives to each line at the output in an uninterrupted
burst with a fixed transport rate of 13.5 MHz. The dura-
tion of the burst is measured in clock periods of the trans-
port clock and is equal to the number of pixels per output
line.
The data transfer is controlled via the signals PIXCLK,
VACT, and LLC. An additional clock signal LLC2 can be
switched to the TDO output pin to support different tim-
ings.
The VACT signal flags the presence of valid output data.
Fig. 2
–
24, 2
–
25, and 2
–
26 illustrate the relationship be-
tween the video port data, VACT, PIXCLK, and LLC.
Whenever a line of video data should be suppressed
(line dropping, switching between analog inputs), it is
done by suppression of VACT.
2.8.1. Single and Double Clock Mode
Data is transferred synchronous to the internally gener-
ated PIXCLK. The frequency of PIXCLK is 13.5 MHz.
The LLC signal is provided as an additional support for
both the 13.5 MHz and the 27 MHz double clock mode.
The LLC consists of a doubled PIXCLK signal (27 MHz)
for interface to external components which rely on the
Philips transfer protocols. In the single clock mode, data
can be latched onto the falling edge of PIXCLK or at the
rising edge of LLC during high PIXCLK. In double clock
mode, output data can be latched onto both clock edges
of PIXCLK or onto every rising edge of LLC. Combined
with the half-clock mode, the available transfer band-
widths at the ports are therefore 6.75 MHz, 13.5 MHz,
and 27.0 MHz.
2.8.2. Clock Gating
To assure a fixed number of clock cycles per line, LLC
and LLC2 can be gated during horizontal blanking. This
mode is enabled when bit[7] of FP-RAM 0x153[refsig] is
set to 1. The start and stop timing is defined by
‘
pval_start
’
and
‘
pval_stop
’
. Note that four additional
LLC cycles are inserted before and after to allow trans-
mission of SAV/EAV headers in ITU-R656 mode.
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