參數(shù)資料
型號(hào)： VPX322XE
廠商： MICRONAS SEMICONDUCTOR HOLDING AG
英文描述： Video Pixel Decoders
中文描述： 視頻解碼器像素
文件頁(yè)數(shù)： 38/92頁(yè)
文件大?。?/td> 567K
代理商： VPX322XE
ADVANCE INFORMATION
VPX 322xE
38
Micronas
2.16. Initialization of the VPX
2.16.1. Power-on-Reset
In order to completely specify the operational mode of
the VPX, appropriate values must be loaded into the I
2
C
and FP registers. After powering the VPX, an internal
power-on-reset clears all the FP/I
2
C-Registers. An ini-
tialization routine loads the default values for both the
I
2
C and FP registers from internal program ROM. The
external RES pin forces all outputs to be tri-stated. At the
inactive going edge of the RES pin, OE and FIELD are
read in for configuration. The FIELD pin is internally
pulled down, an external pull-up resistor could be used
to define a different power-on configuration. The power-
on configuration is read on every rising edge of the exter-
nal RES pin.
Either inactive (tri-state) or active output pins could be
chosen with the FIELD pin at the inactive going edge of
RES. In the inactive state, all relevant output pins are tri-
stated, this includes Port A, Port B, HREF, VREF, FIELD,
VACT, PIXCLK, LLC, and LLC2. In the active setup, all
of these pins are driven. Table 2
–
15 gives an overview
of the different setups. Additionally the data ports A and
B can be tri
–
stated with an external pullup resistor at the
output enable pin OE. The ports can be reactivated ei-
ther by the OE pin or via setting bit[7] in I
2
C register 0xF2
(
”
oeq_dis
”
).
The VPX always comes up in NTSC square pixel mode
(640x240, both fields). In the case of inactive low power
mode, the internal H-Sync scheduler is switched off, as
in normal low power mode. After enabling the chip via
I
2
C Interface, the H-Sync scheduler is enabled and the
chips goes into a normal active NTSC operation condi-
tion.
2.16.2. Software Reset
The VPX provides the possibility of a software reset gen-
erated via I
2
C command (I
2
C register 0xAA, bit[2]). Be
aware that this software reset does not activate the con-
figuration read-in during power-on reset.
2.16.3. Low Power Mode
The VPX goes into low power mode, if the inactive mode
has been chosen. This is equal to the manual chosen
low-power mode. Note, that every manual selection of
the power mode (full or low-power) overwrites (resets!)
the power-up configuration. However, the current con-
figuration cannot be read via the corresponding I
2
C reg-
ister. Other restrictions are that the selection of the low-
power mode limits the rate of the I
2
C-interface to
100 kHz, and that the IC comes up with full power con-
sumption until the low-power circuit becomes active.
Table 2
–
15:
State of the pins during and after reset
Pins
Reset
Active
Inactive
Setup
(FIELD=0)
Active
Setup
(FIELD=1)
Port A
Tri-State
Tri-State
active (OE=0)
Port B
Tri-State
Tri-State
active (OE=0)
HREF
Tri-State
Tri-State
active
VREF
Tri-State
Tri-State
active
FIELD
pull down
Tri-State
active
VACT
Tri-State
Tri-State
active
PIXCLK
Tri-State
Tri-State
active
13.5 MHz
LLC
Tri-State
Tri-State
active
27 MHz
TDO/
LLC2
Tri-State
Tri-State
active
program-
mable output
With the FIELD pin pulled down at the inactive going
edge of RES, the VPX comes up in the low power mode.
This mode is introduced for power consumption critical
applications. It can be turned on and off with bit[1:0] in
the I
2
C register 0xAA (
”
lowpow
”
). There are three levels
of low power mode. When any of them is turned on, the
VPX waits for at least one complete video scan line in or-
der to complete all internal tasks and then goes into tris-
tate mode. The exact moment is not precisely defined,
so care should be taken to deactivate the system using
VPX data before the end of the video scan line in which
the VPX is switched into low power mode. During the low
power mode, all the I
2
C and FP registers are preserved,
so that the VPX restores its normal operation as soon as
low power mode is turned off, without need for any re-ini-
tialization. On the other hand, all the I
2
C and FP regis-
ters can be read/written as usual. The only exception is
the third level (value of 3 in I
2
C register 0xAA) of low
power. In that mode, I
2
C speeds above 100 kbit/sec are
not allowed. In modes 1 and 2, I
2
C can be used up to the
full speed of 400 kbit/s.
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