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參數(shù)資料
| 型號： | VPX322XE |
| 廠商： | MICRONAS SEMICONDUCTOR HOLDING AG |
| 英文描述： | Video Pixel Decoders |
| 中文描述： | 視頻解碼器像素 |
| 文件頁數(shù)： | 41/92頁 |
| 文件大?。?/td> | 567K |
| 代理商： | VPX322XE |
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ADVANCE INFORMATION
VPX 322xE
41
Micronas
2.17.4.3. Self-Test Operation
(Section 12.3.1.b.iii of IEEE 1149.1-1990).
There is no self-test operation included in the VPX de-
sign which is accessible via the TAP.
2.17.4.4. Test Data Registers
(Section 12.3.1.b.iv of IEEE 1149.1-1990).
The VPX includes the use of four test data registers.
They are the required bypass and boundary scan regis-
ters, the optional ID code register, and the master mode
register.
The bypass register is, as defined, a 1-bit register ac-
cessed by codes 100 through 111, inclusive. Since the
design includes the ID code register, the bypass register
is not placed in the serial path upon power-up or Test-
Logic-Reset.
The master mode is an 8-bit test register which is used
to force the VPX
into special test modes. This is reset
upon power-on-reset. This register supports shift and
update only. It is not recommended to access this regis-
ter. The loading of that register can drive the IC into an
undefined state.
2.17.4.5. Boundary Scan Register
(Section 12.3.1.b.v of IEEE 1149.1-1990)
The boundary scan chain has a length of 38 shift regis-
ters. The scan chain order is specified in the section
“
Pin
Connections
”
.
2.17.4.6. Device Identification Register
(Section 12.3.1.b.vi of IEEE 1149.1-1990)
The manufacturer
’
s identification code for Micronas is
“
6C
”
(hex)
. The general implementation scheme uses
only the 7 LSBs and excludes the MSB, which is the par-
ity bit. The part numbers are defined in Table 6
–
2 on
page 71. The version code starts from
“
1
”
(hex)
and
changes with every revision. The version number re-
lates to changes of the chip interface only.
2.17.4.7. Performance
(Section 12.3.1.b.vii of IEEE 1149.1-1990)
See section
“
Specification
”
for further information.
Version
Part Number
Manufacturer ID
31
28 27
12 11
1
0
1
0 0 0 1 0 0 1 1 0 0 1 1 0 1 0 1 x x x x 0 0 0 0 1 1 0 1
0 0
1
7F
8
7
2
3
3
5
x
0
d
9
Fig. 2
–
42:
Device identification register
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