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參數(shù)資料
| 型號： | VPX322XE |
| 廠商： | MICRONAS SEMICONDUCTOR HOLDING AG |
| 英文描述： | Video Pixel Decoders |
| 中文描述： | 視頻解碼器像素 |
| 文件頁數(shù)： | 49/92頁 |
| 文件大?。?/td> | 567K |
| 代理商： | VPX322XE |
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ADVANCE INFORMATION
VPX 322xE
49
Micronas
3.3. Pin Descriptions
Pins 44, 1
–
JTAG Input Pins,
TMS, TDI
(Fig. 3
–
6)
Test Mode Select and Test Data Input signals of the
JTAG Test Access Port (TAP). Both signals are inputs
with a TTL compatible input specification. To comply
with JTAG specification they use pull-ups at their input
stage. The input stage of the TMS and TDI uses a TTL
Schmitt Trigger.
Pin 2
–
JTAG Input Pin,
TCK
(Fig. 3
–
5)
Clock signal of the Test-Access Port. It is used to syn-
chronize all JTAG functions. When JTAG operations are
not being performed, this pin should be driven to VSS.
The input stage of the TCK uses a TTL Schmitt Trigger.
Pin 3
–
JTAG Output Pin,
TDO, LLC2, DACT
(Fig. 3
–
8)
Data output for JTAG Test Access Port (TAP). Moreover
if Test Access Port (TAP) is in Test-Logic-Reset State,
this pin can be used as output pin of the LLC2 clock sig-
nal (I
2
C Reg. 0xF2 bit[4] = 1). Or it can be used as output
pin for the active VBI-Data signal DACT (see section
2.14.).
Pins 4 to 6
–
Reference Signals,
HREF, VREF, FIELD
(Fig. 3
–
8)
These signals are internally generated sync signals. The
state of FIELD during the positive edge of RES selects
the power up mode (see section 2.16.1.).
Pins 7 to 10, 14 to 17
–
Video,
Port A[7:0]
(Fig. 3
–
8)
Video output port to deliver luma and/or chroma data.
Pin 11
–
Supply Voltage (Pad Circuitry),
PVDD
Pins 12, 19
–
Pixel Clock,
PIXCLK
,
LLC
(Fig. 3
–
8)
PIXCLK and LLC are the reference clock signals for the
video data transmission ports A[7:0] and B[7:0].
Pin 13
–
Ground (Pad Circuitry),
PVSS
Pin 18
–
Output Enable Input Signal,
OE
(Fig. 3
–
5)
The output enable input signal has TTL Schmitt Trigger
input characteristic. It controls the tri-state condition of
both video ports. The state during the positive edge of
RES selects the I
2
C device address (see section
2.15.3.).
Pins 20
–
Video Qualifier Output,
VACT
(Fig. 3
–
8)
This pin delivers a signal which qualifies active video
samples.
Pins 21 to 28
–
Video,
Port B[7:0]
(Fig. 3
–
8)
Video output port to deliver chroma data. In 8-bit modes
Port B can be activated as programmable output (see
section 2.7.3.).
Pin 29
–
I
2
C Bus Data,
SDA
(Fig. 3
–
7)
This pin connects to the I
2
C bus data line.
Pin 30
–
I
2
C Bus Clock,
SCL
(Fig. 3
–
7)
This pin connects to the I
2
C bus clock line.
Pin 31
–
Reset Input,
RES
(Fig. 3
–
5)
A low level on this pin resets the VPX 322xE.
Pin 32
–
Ground (Digital Circuitry),
VSS
Pin 33
–
Supply Voltage (Digital Circuitry),
VDD
Pins 34, 35
–
Crystal Input and Output,
XTAL1
,
XTAL2
(Fig. 3
–
10)
These pins are connected to a 20.25 MHz crystal oscilla-
tor which is digitally tuned by integrated shunt capaci-
tances. An external clock can be fed into XTAL1. In this
case, clock frequency adjustment must be switched off.
Pin 36
–
Supply Voltage (Analog Circuitry),
AVDD
Pin 37
–
Chroma Input,
CIN
(Fig. 3
–
14, Fig. 3
–
13)
This pin is connected to the S-VHS chroma signal. A re-
sistive divider is used to bias the input signal to the
middle of the converter input range. CIN can only be
connected to the chroma (Video 2) A/D converter. The
signal must be AC-coupled.
Pin 38
–
Ground (Analog Front-end),
AVSS
Pins 39, 40, 42
–
Video Input 1
–
3,
VIN1
–
3
(Fig. 3
–
12)
These are the analog video inputs. A CVBS, S-VHS
luma signal is converted using the luma (Video 1) A/D
converter. The VIN1 input can also be switched to the
chroma (Video 2) ADC. The input signal must be AC-
coupled.
Pin 41
–
Reference Voltage Top,
VRT
(Fig. 3
–
11)
Via this pin, the reference voltage for the A/D converters
is decoupled. The pin is connected with 10 F/47 nF to
the Signal Ground Pin.
Pin 43
–
Ground (Analog Signal Input),
ISGND
This is the high-quality ground reference for the video
input signals.
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