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參數(shù)資料
| 型號： | VPX322XE |
| 廠商： | MICRONAS SEMICONDUCTOR HOLDING AG |
| 英文描述： | Video Pixel Decoders |
| 中文描述： | 視頻解碼器像素 |
| 文件頁數(shù)： | 18/92頁 |
| 文件大?。?/td> | 567K |
| 代理商： | VPX322XE |
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ADVANCE INFORMATION
VPX 322xE
18
Micronas
2.7. Video Output Interface
Contrary to the component processing stage running at
a clock rate of 20.25 MHz, the output formatting stage
(Fig. 2
–
17) receives the video samples at a pixel trans-
port rate of 13.5 MHz. It supports 8 or 16-bit video for-
mats with separate or embedded reference signals, pro-
vides bus shuffling, and channels the output via one or
both 8-bit ports. Data transfer is synchronous to the in-
ternally generated 13.5 MHz pixel clock.
The format of the output data depends on three parame-
ters:
–
the selected output format
YC
b
C
r
4:2:2, separate syncs
YC
b
C
r
4:2:2, ITU-R656
YC
b
C
r
4:2:2, embedded reference codes (BStream)
–
the number of active ports (A only, or both A and B)
–
clock speed (single, double, half).
In 8-bit modes using only Port A for video data, Port B
can be used as programmable output.
2.7.1. Output Formats
The VPX supports the YC
b
C
r
4:2:2 video format only.
During normal operation, all reference signals are output
separately. To provide a reduced video interface, the
VPX offers two possibilities for encoding timing refer-
ences into the video data stream: an ITU-R656 com-
pliant output format with embedded timing reference
headers and a second format with single timing control
codes in the video stream. The active output format can
be selected via FP-RAM 0x150 [format].
2.7.1.1. YC
b
C
r
4:2:2 with Separate Syncs/ITU-R601
The default output format of the VPX is a synchronous
16-bit YC
b
C
r
4:2:2 data stream with separate reference
signals. Port A is used for luminance and Port B for chro-
minance-information. Video data is compliant to ITU-
R601. Bit[1:0] of FP-RAM 0x150 has to be set to 00. Fig-
ure 2
–
18 shows the timing of the data ports and the
reference signals in this mode.
Fig. 2
–
17:
Output format stage
O
B
O
Clock
Generation
16
8
8
8
8
8
8
Reference
Signals
Video
Samples
Port A
Port B
PIXCLK
LLC
LLC2
HREF
VREF
VACT
OE
8
8
Fig. 2
–
18:
Detailed data output (single clock mode)
Chrominance
(Port B)
VACT
LLC
C
1
C
n
–
1
C
n
Luminance
(Port A)
Y
1
Y
n
–
1
Y
n
PIXCLK
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