參數(shù)資料
型號： W66910
文件頁數(shù)： 3/81頁
文件大?。?/td> 1058K
代理商： W66910
Data Sheet
W66910 PCI ISDN S/T-Controller
Publication Release Date:
Feb,2001
Revision 1.0
-3 -
TABLE OF CONTENTS
1. GENERAL DESCRIPTION
................................................................................................................................................. 8
2. FEATURES
............................................................................................................................................................................ 8
3. PIN CONFIGURATION
..................................................................................................................................................... 9
4. PIN DESCRIPTION
........................................................................................................................................................... 11
5
. SYSTEM DIAGRAM AND APPLICATIONS
................................................................................................................ 13
6. BLOCK DIAGRAM
........................................................................................................................................................... 14
7. FUNCTIONAL DESCRIPTIONS
..................................................................................................................................... 15
7.1 M
AIN
B
LOCK
F
UNCTIONS
................................................................................................................................................... 15
7.2 L
AYER
1 F
UNCTIONS
D
ESCRIPTIONS
................................................................................................................................... 16
7.2.1 S/T Interface Transmitter/Receiver ............................................................................................................................ 16
7.2.2 Receiver Clock Recovery And Timing Generation...................................................................................................... 20
7.2.3 Layer 1 Activation/Deactivation................................................................................................................................ 20
7.2.3.1 States Descriptions And Command/Indication Codes.......................................................................................... 20
7.2.3.2 State Transition Diagrams................................................................................................................................... 22
7.2.4 D Channel Access Control......................................................................................................................................... 26
7.2.5 Frame Alignment....................................................................................................................................................... 26
7.2.5.1 FAinfA_1fr......................................................................................................................................................... 27
7.2.5.2 FAinfB_1fr ......................................................................................................................................................... 27
7.2.5.3 FAinfD_1fr......................................................................................................................................................... 27
7.2.5.4 FAinfA_kfr......................................................................................................................................................... 27
7.2.5.5 FAinfB_kfr ......................................................................................................................................................... 27
7.2.5.6 FAinfD_kfr......................................................................................................................................................... 28
7.2.5.7 Faregain.............................................................................................................................................................. 28
7.2.6 Multiframe Synchronization....................................................................................................................................... 28
7.2.7 Test Functions ........................................................................................................................................................... 29
7.3 S
ERIAL
I
NTERFACE
B
US
..................................................................................................................................................... 31
7.4 B C
HANNEL
S
WITCHING
.................................................................................................................................................... 31
7.5 PCM P
ORT
....................................................................................................................................................................... 33
7.6 D C
HANNEL
HDLC C
ONTROLLER
...................................................................................................................................... 33
7.6.1 D Channel Message Transfer Modes.......................................................................................................................... 34
7.6.2 Reception of Frames in D Channel............................................................................................................................ 34
7.6.3 Transmission of Frames in D Channel....................................................................................................................... 35
7.7 B C
HANNEL
HDLC C
ONTROLLER
...................................................................................................................................... 36
7.7.1 Reception of Frames in B Channel
....................................................................................................................... 36
7.7.2 Transmission of Frames in B Channel........................................................................................................................ 37
7.8 GCI M
ODE
S
ERIAL
I
NTERFACE
B
US
.................................................................................................................................... 38
7.8.1 GCI Mode C/I0 Channel Handling ............................................................................................................................ 39
7.8.2 GCI Mode Monitor Channel Handling....................................................................................................................... 39
7.9 8-
BIT
M
ICROPROSESSOR
I
NTERFACE
C
IRCUIT
...................................................................................................................... 40
7.10 P
ERIPHERAL
C
ONTROL
..................................................................................................................................................... 40
8. REGISTER DESCRIPTIONS ............................................................................................................................................. 42
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