
Data Sheet
W66910 PCI ISDN S/T-Controller
Publication Release Date:
Feb,2001
Revision 1.0
-7 -
LIST OF TABLES
TABLE 4.1 W66910 PIN DESCRIPTIONS ................................................................................................................................11
TABLE 7.1 OUTPUT PHASE DELAY COMPENSATION TABLE...........................................................................................20
TABLE 7.2 LAYER 1 COMMAND CODES..............................................................................................................................22
TABLE 7.3 LAYER 1 INDICATION CODES............................................................................................................................22
TABLE 7.4 D PRIORITY CLASSES..........................................................................................................................................26
TABLE 7.5 D PRIORITY COMMANDS/INDICATIONS ..........................................................................................................26
TABLE 7.6 MULTIFRAME STRUCTURE IN S/T INTERFACE...............................................................................................29
TABLE 8.1 REGISTER ADDRESS MAP: CHIP CONTROL AND D CHANNEL HDLC..........................................................42
TABLE 8.2 REGISTER SUMMARY: CHIP CONTROL AND D CHANNEL HDLC..................................................................43
TABLE 8.3 REGISTER ADDRESS MAP: B1 CHANNEL HDLC..............................................................................................64
TABLE 8.4 REGISTER SUMMARY: B1 CHANNEL HDLC.....................................................................................................65
TABLE 8.5 REGISTER ADDRESS MAP: B2 CHANNEL HDLC..............................................................................................72
TABLE 8.6 REGISTER SUMMARY: B2 CHANNEL HDLC.....................................................................................................72