參數(shù)資料
型號: W66910
文件頁數(shù): 33/81頁
文件大小: 1058K
代理商: W66910
Data Sheet
W66910 PCI ISDN S/T-Controller
Publication Release Date:
Feb,2001
Revision 1.0
-33 -
7.5 PCM Port
There are two PCM ports in W66910. Data is transmitted/ received when PFCK1/PFCK2 is HIGH. The frame synchronization
clocks (PFCK1-2) are 8 kHz and the bit synchronization clock (PBCK) is 1.536 MHz.
7.6 D Channel HDLC Controller
There are two HDLC protocols that are used for ISDN layer 2 functions : LAPD and LAPB. Their frame formats are shown
below.
LAPB modulo 8 :
flag
(1 octet)
(1octet)
(1octet)
(0 or N octets)
(2 octets)
Control field bits
7
6
5
4
3
I frame
N(R)
P
S frame
N(R)
P/F
S
U frame
M
M
M
P/F
M
LAPB modulo 128 :
flag
(1 octet)
(1octet)
(1 or 2 octets)
0 or N octets)
1st octet
Control field bits
7
6
5
4
3
2
1
I frame
N(S)
S frame
X
X
X
X
S
S
0
U frame
M
M
M
P/F
M
M
1
LAPD : modulo 128 only
flag
(1 octet)
(2 octets)
(2 octets)
(0 or N octets)
1st octet
Control field bits
7
6
5
4
3
2
1
I frame
N(S)
S frame
0
0
0
0
S
S
0
U frame
M
M
M
P/F
M
M
1
address
control
information
FCS
flag
(1 octet)
2
1
0
1
0
0
1
1
N(S)
S
M
address
control
information
FCS
(2 octets)
flag
(1 octet)
2nd octet
4
N(R)
N(R)
0
0
1
1
7
6
5
3
2
1
0
P
P/F
address
control
information
FCS
(2 octets)
flag
(1 octet)
2nd octet
4
N(R)
N(R)
0
0
1
1
7
6
5
3
2
1
0
P/F
P/F
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