參數(shù)資料
型號: W66910
文件頁數(shù): 52/81頁
文件大?。?/td> 1058K
代理商: W66910
Data Sheet
W66910 PCI ISDN S/T-Controller
TA20
Publication Release Date:
Feb,2001
Revision 1.0
-52 -
TA27
TA26
TA25
TA24
TA23
TA22
TA21
TA27 - TA20
This register contains the second choice of the second byte address of received frame. For LAPD frame, TA27 - TA21 is the TEI
value, TA20 is EA = 1.
8.1.18 D_ch Receive Frame Byte Count High
Value after reset: 40H
7
6
5
VN1
VN0
LOV
VN1-0 Chip Version Number
This is the chip version number. It is read as 01B.
LOV
Length Overflow
A "1" in this bit indicates
8192 bytes are received and the frame is not yet complete. This bit is valid only after an D_RME
interrupt and remains valid until the frame is acknowledge via the RACK command.
RBC12-8 Receive Byte Count
Four most significant bits of the total frame length. These bits are valid only after an D_RME interrupt and remain valid until the
frame is acknowledge via the RACK command.
D_RBCH
Read Address 11H
4
3
2
1
0
RBC12 RBC11 RBC10
RBC9
RBC8
8.1.19 D_ch Receive Frame Byte Count Low
Value after reset: 00H
7
6
5
RBC7
RBC6
RBC5
RBC7-0 Receive Byte Count
Eight least significant bits of the total frame length. Bits RBC5-0 also indicate the length of the data currently available in
D_RFIFO. These bits are valid only after an D_RME interrupt and remain valid until the frame is acknowledged via the RACK
command.
D_RBCL
Read
Address 12H
4
3
2
1
0
RBC4
RBC3
RBC2
RBC1
RBC0
8.1.20 Timer 2
Value after reset : 00H
7
TMD
TIDLE
TIMR2 Write Address 13H
6
5
4
3
2
1
0
TCN5
TCN4
TCN3
TCN2
TCN1
TCN0
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