The capacitive load (CL
參數(shù)資料
型號: XC3S700A-4FT256I
廠商: Xilinx Inc
文件頁數(shù): 64/132頁
文件大?。?/td> 0K
描述: IC FPGA SPARTAN 3 256FTBGA
標準包裝: 90
系列: Spartan®-3A
LAB/CLB數(shù): 1472
邏輯元件/單元數(shù): 13248
RAM 位總計: 368640
輸入/輸出數(shù): 161
門數(shù): 700000
電源電壓: 1.14 V ~ 1.26 V
安裝類型: 表面貼裝
工作溫度: -40°C ~ 100°C
封裝/外殼: 256-LBGA
供應(yīng)商設(shè)備封裝: 256-FTBGA
DC and Switching Characteristics
DS529-3 (v2.0) August 19, 2010
37
The capacitive load (CL) is connected between the output and GND. The Output timing for all standards, as published in the
speed files and the data sheet, is always based on a CL value of zero. High-impedance probes (less than 1 pF) are used for
all measurements. Any delay that the test fixture might contribute to test measurements is subtracted from those
measurements to produce the final timing numbers as published in the speed files and data sheet.
Differential
LVDS_25
-VICM – 0.125
VICM + 0.125
50
1.2
VICM
LVDS_33
-VICM – 0.125
VICM + 0.125
50
1.2
VICM
BLVDS_25
-VICM – 0.125
VICM + 0.125
1M
0
VICM
MINI_LVDS_25
-VICM – 0.125
VICM + 0.125
50
1.2
VICM
MINI_LVDS_33
-VICM – 0.125
VICM + 0.125
50
1.2
VICM
LVPECL_25
-VICM – 0.3
VICM + 0.3
N/A
VICM
LVPECL_33
-VICM – 0.3
VICM + 0.3
N/A
VICM
RSDS_25
-VICM – 0.1
VICM + 0.1
50
1.2
VICM
RSDS_33
-VICM – 0.1
VICM + 0.1
50
1.2
VICM
TMDS_33
-VICM – 0.1
VICM + 0.1
50
3.3
VICM
PPDS_25
-VICM – 0.1
VICM + 0.1
50
0.8
VICM
PPDS_33
-VICM – 0.1
VICM + 0.1
50
0.8
VICM
DIFF_HSTL_I
-VICM – 0.5
VICM + 0.5
50
0.75
VICM
DIFF_HSTL_III
-VICM – 0.5
VICM + 0.5
50
1.5
VICM
DIFF_HSTL_I_18
-VICM – 0.5
VICM + 0.5
50
0.9
VICM
DIFF_HSTL_II_18
-VICM – 0.5
VICM + 0.5
50
0.9
VICM
DIFF_HSTL_III_18
-VICM – 0.5
VICM + 0.5
50
1.8
VICM
DIFF_SSTL18_I
-VICM – 0.5
VICM + 0.5
50
0.9
VICM
DIFF_SSTL18_II
-VICM – 0.5
VICM + 0.5
50
0.9
VICM
DIFF_SSTL2_I
-VICM – 0.5
VICM + 0.5
50
1.25
VICM
DIFF_SSTL2_II
-VICM – 0.5
VICM + 0.5
50
1.25
VICM
DIFF_SSTL3_I
-VICM – 0.5
VICM + 0.5
50
1.5
VICM
DIFF_SSTL3_II
-VICM – 0.5
VICM + 0.5
50
1.5
VICM
Notes:
1.
Descriptions of the relevant symbols are as follows:
VREF – The reference voltage for setting the input switching threshold
VICM – The common mode input voltage
VM – Voltage of measurement point on signal transition
VL – Low-level test voltage at Input pin
VH – High-level test voltage at Input pin
RT – Effective termination resistance, which takes on a value of 1 MΩ when no parallel termination is required
VT – Termination voltage
2.
The load capacitance (CL) at the Output pin is 0 pF for all signal standards.
3.
According to the PCI specification.
Table 27: Test Methods for Timing Measurement at I/Os(Continued)
Signal Standard
(IOSTANDARD)
Inputs
Outputs
Inputs and
Outputs
VREF (V)
VL (V)
VH (V)
RT (Ω)VT (V)
VM (V)
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