參數(shù)資料
型號: XC3S700A-4FT256I
廠商: Xilinx Inc
文件頁數(shù): 80/132頁
文件大?。?/td> 0K
描述: IC FPGA SPARTAN 3 256FTBGA
標準包裝: 90
系列: Spartan®-3A
LAB/CLB數(shù): 1472
邏輯元件/單元數(shù): 13248
RAM 位總計: 368640
輸入/輸出數(shù): 161
門數(shù): 700000
電源電壓: 1.14 V ~ 1.26 V
安裝類型: 表面貼裝
工作溫度: -40°C ~ 100°C
封裝/外殼: 256-LBGA
供應(yīng)商設(shè)備封裝: 256-FTBGA
DC and Switching Characteristics
DS529-3 (v2.0) August 19, 2010
51
Phase Shifter (PS)
Table 40: Recommended Operating Conditions for the PS in Variable Phase Mode
Symbol
Description
Speed Grade
Units
-5
-4
Min
Max
Min
Max
Operating Frequency Ranges
PSCLK_FREQ
(FPSCLK)
Frequency for the PSCLK input
1
167
1
167
MHz
Input Pulse Requirements
PSCLK_PULSE
PSCLK pulse width as a percentage of the PSCLK period
40%
60%
40%
60%
-
Table 41: Switching Characteristics for the PS in Variable Phase Mode
Symbol
Description
Phase Shift Amount
Units
Phase Shifting Range
MAX_STEPS(2)
Maximum allowed number of
DCM_DELAY_STEP steps for a
given CLKIN clock period, where
T = CLKIN clock period in ns. If using
CLKIN_DIVIDE_BY_2 = TRUE,
double the clock effective clock
period.
CLKIN < 60
MHz
±[INTEGER(10
(T
CLKIN – 3 ns))]
steps
CLKIN
60
MHz
±[INTEGER(15
(T
CLKIN – 3 ns))]
FINE_SHIFT_RANGE_MIN
Minimum guaranteed delay for variable phase shifting
±[MAX_STEPS
DCM_DELAY_STEP_MIN]
ns
FINE_SHIFT_RANGE_MAX
Maximum guaranteed delay for variable phase shifting
±[MAX_STEPS
DCM_DELAY_STEP_MAX]
ns
Notes:
1.
The numbers in this table are based on the operating conditions set forth in Table 8 and Table 40.
2.
The maximum variable phase shift range, MAX_STEPS, is only valid when the DCM is has no initial fixed phase shifting, that is, the
PHASE_SHIFT attribute is set to 0.
3.
The DCM_DELAY_STEP values are provided at the bottom of Table 37.
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