參數(shù)資料
型號： XCF128XFTG64C
廠商： Xilinx Inc
文件頁數(shù)： 5/88頁
文件大?。?/td> 0K
描述： IC PROM SRL 128M GATE 64-FTBGA
標準包裝： 1
可編程類型： 系統(tǒng)內(nèi)可編程
存儲容量： 128Mb
電源電壓： 1.7 V ~ 2 V
工作溫度： -40°C ~ 85°C
封裝/外殼： 64-TBGA
供應(yīng)商設(shè)備封裝： 64-TFBGA
包裝： 托盤
產(chǎn)品目錄頁面： 601 (CN2011-ZH PDF)
其它名稱： 122-1578
Platform Flash XL High-Density Configuration and Storage Device
DS617 (v3.0.1) January 07, 2010
Product Specification
13
R
into Read Electronic Signature mode. Subsequent Bus
Read cycles output Electronic Signature data, and the
Program/Erase controller continues to program or erase in
the background.
The Read Electronic Signature command only changes the
read mode of the addressed bank. The read modes of other
banks are not affected. Only Asynchronous Read and
Single Synchronous Read operations should be used to
read the Electronic Signature. A Read Array command is
required to return the bank to Read Array mode.
Read CFI Query Command
The Read CFI Query command is used to read data from
the Common Flash Interface (CFI). One Bus Write cycle is
required to issue the Read CFI Query command. After a
bank is in Read CFI Query mode, subsequent Bus Read
operations in the same bank read from the Common Flash
Interface. The Read CFI Query command can be issued at
any time, even during program or erase operations.
If a Read CFI Query command is issued to a bank executing
a program or erase operation, the bank enters into Read
CFI Query mode. Subsequent Bus Read cycles output CFI
data, and the Program/Erase controller continues to
program or erase in the background.
The Read CFI Query command only changes the read
mode of the addressed bank. The read modes of other
banks are not affected. Only Asynchronous Read and
Single Synchronous Read operations should be used to
read from the CFI. A Read Array command is required to
return the bank to Read Array mode. Dual operations
between the Parameter Bank and the CFI memory space
are not allowed (see Table 17, page 36 for details).
See "Appendix B: Common Flash Interface," page 65,
Table 36, page 65, through Table 45, page 70, Table 38,
Table 38 for details on the information contained in the
Common Flash Interface memory area.
Clear Status Register Command
The Clear Status Register command can be used to reset
(set to ‘0’) all error bits (SR1, 3, 4 and 5) in the Status
Register. One Bus Write cycle is required to issue the Clear
Status Register command. The Clear Status Register
command does not affect the read mode of the bank.
The error bits in the Status Register do not automatically
return to ‘0’ when a new command is issued. The error bits
in the Status Register should be cleared before attempting a
new program or erase command.
Block Erase Command
The Block Erase command is used to erase a block. It sets
all the bits within the selected block to ‘1’. All previous data
in the block is lost.
If the block is protected, then the erase operation aborts,
data in the block is not changed, and the Status Register
outputs the error.
Two Bus Write cycles are required to issue the command.
The first bus cycle sets up the Block Erase command.
The second latches the block address and starts the
Program/Erase Controller.
If the second bus cycle is not the Block Erase Confirm code,
Status Register bits SR4 and SR5 are set and the
command is aborted.
After the command is issued, the bank enters Read Status
Register mode, and any read operation within the
addressed bank outputs the contents of the Status Register.
A Read Array command is required to return the bank to
Read Array mode.
During Block Erase operations, the bank containing the
block being erased only accepts the Read Array, Read
Status Register, Read Electronic Signature, Read CFI
Query, and Program/Erase Suspend command; all other
commands are ignored.
The Block Erase operation aborts if Reset (RP) goes to VIL.
As data integrity cannot be guaranteed when the Block
Erase operation is aborted, the block must be erased again.
Refer to "Dual Operations and Multiple Bank Architecture,"
page 35 for detailed information about simultaneous
operations allowed in banks not being erased.
Typical Erase times are given in Table 21, page 44.
See Figure 41, page 75, for a suggested flowchart for using
the Block Erase command.
Blank Check Command
The Blank Check command is used to check whether a Block
is completely erased. Only one block at a time can be
checked. To use the Blank Check command, VPP must be
equal to VPPH. If VPP is not equal to VPPH, the device ignores
the command and no error is shown in the Status Register.
Two bus cycles are required to issue the Blank Check
command:
The first bus cycle writes the Blank Check command
(BCh) to any address in the block to be checked.
The second bus cycle writes the Blank Check Confirm
command (CBh) to any address in the block to be
checked and starts the Blank Check operation.
If the second bus cycle is not Blank Check Confirm,
Status Register bits SR4 and SR5 are set to '1', and the
command aborts.
After the command is issued, the addressed bank
automatically enters the Status Register mode and further
reads within the bank output the Status Register contents.
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