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參數(shù)資料
| 型號： | XIO2200AZGW |
| 廠商： | Texas Instruments |
| 文件頁數(shù)： | 131/202頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC PCI-EXPRESS/BUS BRIDGE 176BGA |
| 產(chǎn)品培訓模塊： | PCI Express Basics |
| 標準包裝： | 126 |
| 應用： | PCI Express 至 PCI 轉(zhuǎn)換橋 |
| 接口： | PCI |
| 電源電壓： | 1.35 V ~ 1.65 V，3 V ~ 3.6 V |
| 封裝/外殼： | 176-LFBGA |
| 供應商設備封裝： | 176-BGA MICROSTAR（15x15） |
| 包裝： | 托盤 |
| 安裝類型： | 表面貼裝 |
| 產(chǎn)品目錄頁面： | 882 (CN2011-ZH PDF) |
| 配用： | XIO2200AEVM-ND - XIO2200AEVM |
| 其它名稱： | 296-19567 |
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Feature/Protocol Descriptions
21
March 5 2007 June 2011
SCPS154C
Table 31. Bridge Reset Options
RESET OPTION
XIO2200A FEATURE
RESET RESPONSE
Bridge
internally-generated
power-on reset
During a power-on cycle, the bridge asserts an internal
reset and monitors the VDD_15_COMB (M17) terminal.
When this terminal reaches 90% of the nominal input
voltage specification, power is considered stable. After
stable power, the bridge monitors the PCI Express
reference clock (REFCLK) and waits 10 μs after active
clocks are detected. Then, internal power-on reset is
deasserted.
When the internal power-on reset is asserted, all control
registers, state machines, sticky register bits, and power
management state machines are initialized to their
default state.
In addition, the bridge asserts the internal PCI bus reset.
Global reset input
GRST (N17)
When GRST is asserted low, an internal power-on reset
occurs. This reset is asynchronous and functions during
both normal power states and VAUX power states.
When GRST is asserted low, all control registers, state
machines, sticky register bits, and power management
state machines are initialized to their default state.
In addition, the bridge asserts the internal PCI bus reset.
When the rising edge of GRST occurs, the bridge
samples the state of all static control inputs and latches
the information internally. If an external serial EEPROM
is detected, then a download cycle is initiated. Also, the
process to configure and initialize the PCI Express link is
started. The bridge starts link training within 80 ms after
GRST is deasserted.
PCI Express reset
input PERST (J17)
This bridge input terminal is used by an upstream PCI
Express device to generate a PCI Express reset and to
signal a system power good condition.
When PERST is asserted low, the bridge generates an
internal PCI Express reset as defined in the PCI Express
specification.
When PERST transitions from low to high, a system
power good condition is assumed by the bridge.
Note: The system must assert PERST before power is
removed, before REFCLK is removed or before
REFCLK becomes unstable.
When PERST is asserted low, all control register bits
that are not sticky are reset. Within the configuration
register maps, the sticky bits are indicated by the k
symbol. Also, all state machines that are not associated
with sticky functionality or VAUX power management are
reset.
In addition, the bridge asserts the internal PCI bus reset.
When the rising edge of PERST occurs, the bridge
samples the state of all static control inputs and latches
the information internally. If an external serial EEPROM
is detected, then a download cycle is initiated. Also, the
process to configure and initialize the PCI Express link is
started. The bridge starts link training within 80 ms after
PERST is deasserted.
PCI Express training
control hot reset
The bridge responds to a training control hot reset
received on the PCI Express interface. After a training
control hot reset, the PCI Express interface enters the
DL_DOWN state.
In the DL_DOWN state, all remaining configuration
register bits and state machines are reset. All remaining
bits exclude sticky bits and EEPROM loadable bits. All
remaining state machines exclude sticky functionality,
EEPROM functionality, and VAUX power management.
Within the configuration register maps, the sticky bits are
indicated by the k symbol and the EEPROM loadable
bits are indicated by the symbol.
In addition, the bridge asserts the internal PCI bus reset.
PCI bus reset
System software has the ability to assert and deassert
the PCI bus reset on the secondary PCI bus interface.
When bit 6 (SRST) in the bridge control register at offset
3Eh (see Section 4.29) is asserted, the bridge asserts
the internal PCI bus reset. A 0b in the SRST bit
deasserts the PCI bus reset.
3.3
PCI Express Interface
3.3.1 External Reference Clock
The bridge requires either a differential, 100-MHz common clock reference or a single-ended, 125-MHz clock
reference. The selected clock reference must meet all PCI Express Electrical Specification requirements for
frequency tolerance, spread spectrum clocking, and signal electrical characteristics.
Not Recommended for New Designs
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| XIO2200AZGW | 制造商:Texas Instruments 功能描述:PCI Express to PCI Bus Converter IC |
| XIO2200AZHH | 功能描述:外圍驅(qū)動器與原件 - PCI PCI Exp-PCI Bus Trans Bridge RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| XIO2200GGW | 功能描述:IC PCI-EXPRESS/BUS BRIDGE 176BGA RoHS:是 類別:集成電路 (IC) >> 接口 - 專用 系列:- 標準包裝:3,000 系列:- 應用:PDA，便攜式音頻/視頻，智能電話 接口:I²C，2 線串口 電源電壓:1.65 V ~ 3.6 V 封裝/外殼:24-WQFN 裸露焊盤 供應商設備封裝:24-QFN 裸露焊盤（4x4） 包裝:帶卷 (TR) 安裝類型:表面貼裝 產(chǎn)品目錄頁面:1015 (CN2011-ZH PDF) 其它名稱:296-25223-2 |
| XIO2200ZGW | 功能描述:IC PCI-EXPRESS/BUS BRIDGE 176BGA RoHS:是 類別:集成電路 (IC) >> 接口 - 專用 系列:- 標準包裝:3,000 系列:- 應用:PDA，便攜式音頻/視頻，智能電話 接口:I²C，2 線串口 電源電壓:1.65 V ~ 3.6 V 封裝/外殼:24-WQFN 裸露焊盤 供應商設備封裝:24-QFN 裸露焊盤（4x4） 包裝:帶卷 (TR) 安裝類型:表面貼裝 產(chǎn)品目錄頁面:1015 (CN2011-ZH PDF) 其它名稱:296-25223-2 |
| XIO2213A | 制造商:TI 制造商全稱:Texas Instruments 功能描述:XIO2213A PCI Express to 1394b OHCI with 3-Port PHY |
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