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參數(shù)資料
| 型號： | XIO2200AZGW |
| 廠商： | Texas Instruments |
| 文件頁數(shù)： | 146/202頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC PCI-EXPRESS/BUS BRIDGE 176BGA |
| 產(chǎn)品培訓(xùn)模塊： | PCI Express Basics |
| 標準包裝： | 126 |
| 應(yīng)用： | PCI Express 至 PCI 轉(zhuǎn)換橋 |
| 接口： | PCI |
| 電源電壓： | 1.35 V ~ 1.65 V，3 V ~ 3.6 V |
| 封裝/外殼： | 176-LFBGA |
| 供應(yīng)商設(shè)備封裝： | 176-BGA MICROSTAR（15x15） |
| 包裝： | 托盤 |
| 安裝類型： | 表面貼裝 |
| 產(chǎn)品目錄頁面： | 882 (CN2011-ZH PDF) |
| 配用： | XIO2200AEVM-ND - XIO2200AEVM |
| 其它名稱： | 296-19567 |
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Feature/Protocol Descriptions
35
March 5 2007 June 2011
SCPS154C
3.9
General-Purpose I/O Interface
Up to eight general-purpose input/output (GPIO) terminals are provided for system customization. These
GPIO terminals are 3.3-V tolerant.
The exact number of GPIO terminals varies based on implementing the clock run, power override, and serial
EEPROM interface features. These features share four of the eight GPIO terminals. When any of the three
shared functions are enabled, the associated GPIO terminal is disabled.
All eight GPIO terminals are individually configurable as either inputs or outputs by writing the corresponding
bit in the GPIO control register at offset B4h. A GPIO data register at offset B6h exists to either read the logic
state of each GPIO input or to set the logic state of each GPIO output. The power-up default state for the GPIO
control register is input mode.
3.10 Set Slot Power Limit Functionality
The PCI Express Specification provides a method for devices to limit internal functionality and save power
based on the value programmed into the captured slot power limit scale (CSPLS) and capture slot power limit
value (CSPLV) fields of the PCI Express device capabilities register at offset 94h. See Section 4.49, Device
Capabilities Register, for details. The bridge writes these fields when a set slot power limit message is received
on the PCI Express interface.
After the deassertion of PERST, the XIO2200A compares the information within the CSPLS and CSPLV fields
of the device capabilities register to the minimum power scale (MIN_POWER_SCALE) and minimum power
value (MIN_POWER_VALUE) fields in the general control register at offset D4h. See Section 4.65, General
Control Register, for details. If the CSPLS and CSPLV fields are less than the MIN_POWER_SCALE and
MIN_POWER_VALUE fields, respectively, then the bridge takes the appropriate action that is defined below.
The power usage action is programmable within the bridge. The general control register includes a 3-bit
PWR_OVRD field. This field is programmable to the following two options:
1. Ignore slot power limit fields
2. Respond with unsupported request to all transactions except type 0/1 configuration transactions and set
slot power limit messages
3.11 PCI Express and PCI Bus Power Management
The bridge supports both software-directed power management and active state power management through
standard PCI configuration space. Software-directed registers are located in the power management
capabilities structure located at offset 50h. Active state power management control registers are located in
the PCI Express capabilities structure located at offset 90h.
During software-directed power management state changes, the bridge initiates link state transitions to L1 or
L2/L3 after a configuration write transaction places the device in a low power state. The power management
state machine is also responsible for gating internal clocks based on the power state. Table 312 identifies
the relationship between the D-states and bridge clock operation.
Table 312. Clocking In Low Power States
CLOCK SOURCE
D0/L0
D1/L1
D2/L1
D3/L2/L3
PCI express reference clock input (REFCLK)
On
On/Off
Internal PCI bus clock to bridge function
On
Off
Internal PCI bus clock to 1394a OHCI function
On
On/Off
The link power management (LPM) state machine manages active state power by monitoring the PCI Express
transaction activity. If no transactions are pending and the transmitter has been idle for at least the minimum
time required by the PCI Express Specification, then the LPM state machine transitions the link to either the
L0s or L1 state. By reading the bridge’s L0s and L1 exit latency in the link capabilities register, the system
software may make an informed decision relating to system performance versus power savings. The ASLPMC
field in the link control register provides an L0s only option, L1 only option, or both L0s and L1 option.
Not Recommended for New Designs
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XIO2200AZGW | 制造商:Texas Instruments 功能描述:PCI Express to PCI Bus Converter IC |
| XIO2200AZHH | 功能描述:外圍驅(qū)動器與原件 - PCI PCI Exp-PCI Bus Trans Bridge RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| XIO2200GGW | 功能描述:IC PCI-EXPRESS/BUS BRIDGE 176BGA RoHS:是 類別:集成電路 (IC) >> 接口 - 專用 系列:- 標準包裝:3,000 系列:- 應(yīng)用:PDA，便攜式音頻/視頻，智能電話 接口:I²C，2 線串口 電源電壓:1.65 V ~ 3.6 V 封裝/外殼:24-WQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:24-QFN 裸露焊盤（4x4） 包裝:帶卷 (TR) 安裝類型:表面貼裝 產(chǎn)品目錄頁面:1015 (CN2011-ZH PDF) 其它名稱:296-25223-2 |
| XIO2200ZGW | 功能描述:IC PCI-EXPRESS/BUS BRIDGE 176BGA RoHS:是 類別:集成電路 (IC) >> 接口 - 專用 系列:- 標準包裝:3,000 系列:- 應(yīng)用:PDA，便攜式音頻/視頻，智能電話 接口:I²C，2 線串口 電源電壓:1.65 V ~ 3.6 V 封裝/外殼:24-WQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:24-QFN 裸露焊盤（4x4） 包裝:帶卷 (TR) 安裝類型:表面貼裝 產(chǎn)品目錄頁面:1015 (CN2011-ZH PDF) 其它名稱:296-25223-2 |
| XIO2213A | 制造商:TI 制造商全稱:Texas Instruments 功能描述:XIO2213A PCI Express to 1394b OHCI with 3-Port PHY |
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