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| 型號(hào)： | XIO2200AZGW |
| 廠商： | Texas Instruments |
| 文件頁(yè)數(shù)： | 96/202頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC PCI-EXPRESS/BUS BRIDGE 176BGA |
| 產(chǎn)品培訓(xùn)模塊： | PCI Express Basics |
| 標(biāo)準(zhǔn)包裝： | 126 |
| 應(yīng)用： | PCI Express 至 PCI 轉(zhuǎn)換橋 |
| 接口： | PCI |
| 電源電壓： | 1.35 V ~ 1.65 V，3 V ~ 3.6 V |
| 封裝/外殼： | 176-LFBGA |
| 供應(yīng)商設(shè)備封裝： | 176-BGA MICROSTAR（15x15） |
| 包裝： | 托盤 |
| 安裝類型： | 表面貼裝 |
| 產(chǎn)品目錄頁(yè)面： | 882 (CN2011-ZH PDF) |
| 配用： | XIO2200AEVM-ND - XIO2200AEVM |
| 其它名稱： | 296-19567 |
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1394 PHY Configuration Space
172
March 5 2007 June 2011
SCPS154C
Table 102. Base Register Field Descriptions (Continued)
FIELD
SIZE
TYPE
DESCRIPTION
ISBR
1
RW
Initiate short arbitrated bus reset. This bit, if set to 1b, instructs the PHY layer to initiate a short (1.3 μs)
arbitrated bus reset at the next opportunity. This bit is cleared to 0b by a bus reset.
Note: Legacy IEEE Std 1394-1995 compliant PHY layers can not be capable of performing short bus resets.
Therefore, initiation of a short bus reset in a network that contains such a legacy device results in a long bus
reset being performed.
Loop
1
RW
Loop detect. This bit is set to 1b when the arbitration controller times out during tree-ID start and may indicate
that the bus is configured in a loop. This bit is cleared to 0b by system (hardware) reset or by writing a 1b to
this register bit.
If the Loop and Watchdog bits are both set and the LLC is or becomes inactive, then the PHY layer activates
the LLC to service the interrupt.
Note: If the network is configured in a loop, then only those nodes which are part of the loop generate a
configuration-timeout interrupt. All other nodes instead time out waiting for the tree-ID and/or self-ID process
to complete and then generate a state time-out interrupt and bus-reset.
Pwr_fail
1
RW
Cable power failure detect. This bit is set to 1b whenever the CPS input transitions from high to low indicating
that cable power may be too low for reliable operation. This bit is cleared to 0b by system (hardware) reset or
by writing a 1b to this register bit.
Timeout
1
RW
State time-out interrupt. This bit indicates that a state time-out has occurred (which also causes a bus reset to
occur). This bit is cleared to 0b by system (hardware) reset or by writing a 1b to this register bit.
Port_event
1
RW
Port event detect. This bit is set to 1b upon a change in the bias (unless disabled) connected, disabled, or
fault bits for any port for which the port interrupt enable (Int_enable) bit is set. Additionally, if the Watchdog bit
is set, then the Port_event bit is set to 1b at the start of resume operations on any port. This bit is cleared to 0b
by system (hardware) reset or by writing a 1b to this register bit.
Enab_accel
1
RW
Enable accelerated arbitration. This bit enables the PHY layer to perform the various arbitration acceleration
enhancements defined in IEEE Std 1394a-2000 (ACK-accelerated arbitration, asynchronous fly-by
concatenation, and isochronous fly-by concatenation). This bit is cleared to 0b by system (hardware) reset
and is unaffected by bus reset.
Enab_multi
1
RW
Enable multispeed concatenated packets. This bit enables the PHY layer to transmit concatenated packets
of differing speeds in accordance with the protocols defined in IEEE Std 1394a-2000. This bit is cleared to 0b
by system (hardware) reset and is unaffected by bus reset.
Page_Select
3
RW
Page_Select. This field selects the register page to use when accessing register addresses 8 through 15.
This field is cleared to 000b by a system (hardware) reset and is unaffected by bus reset.
Port_Select
4
RW
Port_Select. This field selects the port when accessing per-port status or control (for example, when one of
the port status/control registers is accessed in page 0). Ports are numbered starting at 0. This field is cleared
to 0h by system (hardware) reset and is unaffected by bus reset.
These bits are reset by a PCI Express reset (PERST), a GRST, or the internally-generated power-on reset.
Not Recommended for New Designs
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XIO2200AZGW | 制造商:Texas Instruments 功能描述:PCI Express to PCI Bus Converter IC |
| XIO2200AZHH | 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI PCI Exp-PCI Bus Trans Bridge RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| XIO2200GGW | 功能描述:IC PCI-EXPRESS/BUS BRIDGE 176BGA RoHS:是 類別:集成電路 (IC) >> 接口 - 專用 系列:- 標(biāo)準(zhǔn)包裝:3,000 系列:- 應(yīng)用:PDA，便攜式音頻/視頻，智能電話 接口:I²C，2 線串口 電源電壓:1.65 V ~ 3.6 V 封裝/外殼:24-WQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:24-QFN 裸露焊盤（4x4） 包裝:帶卷 (TR) 安裝類型:表面貼裝 產(chǎn)品目錄頁(yè)面:1015 (CN2011-ZH PDF) 其它名稱:296-25223-2 |
| XIO2200ZGW | 功能描述:IC PCI-EXPRESS/BUS BRIDGE 176BGA RoHS:是 類別:集成電路 (IC) >> 接口 - 專用 系列:- 標(biāo)準(zhǔn)包裝:3,000 系列:- 應(yīng)用:PDA，便攜式音頻/視頻，智能電話 接口:I²C，2 線串口 電源電壓:1.65 V ~ 3.6 V 封裝/外殼:24-WQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:24-QFN 裸露焊盤（4x4） 包裝:帶卷 (TR) 安裝類型:表面貼裝 產(chǎn)品目錄頁(yè)面:1015 (CN2011-ZH PDF) 其它名稱:296-25223-2 |
| XIO2213A | 制造商:TI 制造商全稱:Texas Instruments 功能描述:XIO2213A PCI Express to 1394b OHCI with 3-Port PHY |
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