參數(shù)資料
型號(hào)： XR88C681P/40-F
廠商： Exar Corporation
文件頁數(shù)： 29/101頁
文件大小： 0K
描述： IC UART CMOS DUAL 40PDIP
標(biāo)準(zhǔn)包裝： 9
特點(diǎn)： *
通道數(shù)： 2，DUART
FIFO's： 1 字節(jié)，3 字節(jié)
電源電壓： 4.75 V ~ 5.25 V
帶并行端口： 是
帶CMOS： 是
安裝類型： 通孔
封裝/外殼： 40-DIP（0.600"，15.24mm）
供應(yīng)商設(shè)備封裝： 40-PDIP
包裝： 管件
其它名稱： 1016-1640
XR88C681P/40-F-ND
XR88C681
33
Rev. 2.11
Input Name
Trigger
Priority
Type
Acknowledge
Signal?
Address (Hex)
RST 7.5
Positive Edge Triggered
2
Direct
None
003C
RST 6.5
High Level Until Sampled
3
Direct
None
0034
RST 5.5
High Level Until Sampled
4
Direct
None
002C
INTR
High Level Until Sampled
5
External Vectored
-
INTA = “Low”
See
Table 10
Table 11. 8085 CPU Maskable Interrupt Request Inputs and their Features
Direct Interrupts
The 8085 CPU inputs RST 7.5, RST 6.5, and RST 5.5 are
“Direct Interrupt” request inputs. Specifically, if any of
these inputs are asserted, then the program counter of
the CPU is, upon completion of the current instruction,
automatically
loaded
with
a
memory
location
(pre-determined by the circuitry within the 8085 device),
and branches program control to that location. These
“Direct” interrupts do not provide the peripheral device
with any sort of “Interrupt Acknowledge”.
Hence,
according to
Table 11, if the RST 7.5 input were asserted,
the value “003C16” would be loaded into the program
counter of the CPU, and program control would branch to
that location in memory. The user is responsible to insure
that the correct interrupt service routine begins at that
location in memory.
The 8085 CPU offers interrupt prioritization, within the set
of Maskable Interrupts. This priority is reflected
Table 11.
It should be noted that these priority levels only apply to
“pending” interrupt request. Once a particular interrupt
has “l(fā)eft the queue” and is being serviced by the CPU, this
prioritization scheme no longer applies to that particular
interrupt. Consequently, it is possible that an RST 5.5
interrupt request could “interrupt” the interrupt service
routine for the higher priority RST 7.5 interrupt request.
Therefore, the user must guard against this phenomenon
in his/her firmware.
Table 11 also indicates that the 8085 CPU will support
“external” vectored interrupts.
The manner and
commands that are used in external vectored interrupt
processing are identical to that presented for the 8080
CPU (see
Section C.6.1.2).
Figure 10
and
Figure 11
present
two
different
approaches that can be used to interface the XR88C681
DUART to the 8085 CPU.
Figure 10 presents a schematic where the DUART will
request a “Direct” RST 6.5 Interrupt to the 8085 CPU. In
this case, the Interrupt Service Routine for the DUART
must begin at 003416 in system memory. This is a very
simple interface technique, because there is no “Interrupt
Acknowledge” signal to route and interface.
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