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參數(shù)資料
| 型號： | XR88C681P/40-F |
| 廠商： | Exar Corporation |
| 文件頁數(shù)： | 33/101頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC UART CMOS DUAL 40PDIP |
| 標(biāo)準(zhǔn)包裝： | 9 |
| 特點(diǎn)： | * |
| 通道數(shù)： | 2，DUART |
| FIFO's： | 1 字節(jié)，3 字節(jié) |
| 電源電壓： | 4.75 V ~ 5.25 V |
| 帶并行端口： | 是 |
| 帶CMOS： | 是 |
| 安裝類型： | 通孔 |
| 封裝/外殼： | 40-DIP（0.600"，15.24mm） |
| 供應(yīng)商設(shè)備封裝： | 40-PDIP |
| 包裝： | 管件 |
| 其它名稱： | 1016-1640 XR88C681P/40-F-ND |
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XR88C681
37
Rev. 2.11
Accumulator. Three of the input pins support input
capture functions; and four of the output pins support
output compare functions.
Port B
Port B consists of 8 output pins. If the 68HC11 C is
operating in the single chip mode, this port functions as a
general purpose output port. However, if the 68HC11 is
operating in the expanded-multiplexed mode, then this
port will function as the upper address byte for
memory/peripheral device interfacing (A8 - A15).
Port C
Port C consists of 8 bi-directional pins. When the 68HC11
is operating in the single-chip mode, this port functions as
a general purpose bi-directional port. However, if the
68HC11 is operating in the expanded-multiplexed mode
then this port will function as the multiplexed address/data
bus (AD0 - AD7). Specifically, during the first half of a
memory cycle, this port will function as the lower address
byte (Port B is the upper address byte) for addressing
memory devices and peripheral components. During the
second half of the memory cycle, this port will function as
the bi-directional data bus.
This port can be
demultiplexed via the use of the AS (Address Strobe) pin
and a 74LS373 latch device.
Port D
Port D consists of 8 bi-directional pins. However, this port
can be configured to support the on-chip Serial Peripheral
Interface (SPI), and Serial Communications Interface
(SCI).
Port E
Port E consists of either 4 or 8 inputs (depending upon the
packaging option). This port can be configured to function
as a general purpose input or as the inputs to the on-chip
A/D converter.
There are numerous other pins that are pertinent for
interfacing to the XR88C681 DUART device. Some of
these pins are discussed here.
IRQ
This is the “maskable” interrupt request input. If this input
is asserted (e.g., toggled “l(fā)ow”), then the 68HC11 C will
branch program control to FFF2, FFF3 in system memory
(on-chip ROM). The user is responsible for insuring that
the appropriate interrupt service routine resides at this
location in memory.
AS/STRA
AS or “Address Strobe” can be used to demultiplex the
address/data bus of Port C. This pin is at a logic “high”
during the first half of a memory cycle; and at a logic “l(fā)ow”
during the second half of a memory cycle.
If the 68HC11 is intended to operate in the
expanded-multiplexed mode and interface to more than
256 bytes of addressable memory space, then both Ports
B and C are required as shown in
Figure 13. Figure 13
also illustrates how the XR88C681 DUART could be
connected to the 68HC11
C for interrupt driven
operation. If the DUART requests an interrupt, its active
low -INTR pin will be asserted (toggle low), which will, in
turn, cause the -IRQ pin of the CPU to be asserted. When
this occurs the C will continue executing its current
instruction. After completion of this instruction, program
control will shift to location FFF2, FFF3 in system
memory. The user is responsible to insure that the
DUART’s interrupt service routine resides at this location
in memory.
The
C will not issue an interrupt
acknowledge signal to the DUART. Instead, the C will
just processes through the interrupt service routine.
Once the C has eliminated the cause(s) of the DUART’s
interrupt request, the -INTR pin will be negated and the C
will return from the Interrupt Service Routine and resume
normal processing.
One more point should be mentioned about
Figure 13.
The glue-logic circuitry required to generate the -WR,
-RD, and the RESET signals for the DUART, from the
-R/W, -RESET, and E clock presented in
Figure 2. This
circuitry has also been included in
Figure 14.
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