INTR output. This action will, in turn, cause the -INT input
參數(shù)資料
型號(hào)： XR88C681P/40-F
廠商： Exar Corporation
文件頁(yè)數(shù)： 42/101頁(yè)
文件大小： 0K
描述： IC UART CMOS DUAL 40PDIP
標(biāo)準(zhǔn)包裝： 9
特點(diǎn)： *
通道數(shù)： 2，DUART
FIFO's： 1 字節(jié)，3 字節(jié)
電源電壓： 4.75 V ~ 5.25 V
帶并行端口： 是
帶CMOS： 是
安裝類型： 通孔
封裝/外殼： 40-DIP（0.600"，15.24mm）
供應(yīng)商設(shè)備封裝： 40-PDIP
包裝： 管件
其它名稱： 1016-1640
XR88C681P/40-F-ND
XR88C681
45
Rev. 2.11
-
INTR output. This action will, in turn, cause the -INT input
of the CPU to be asserted. Once the CPU has completed
its current instruction, the CPU Module will assert the
-
INTA signal. This will in turn assert the -IACK (Interrupt
Acknowledge) input to the DUART. The purpose of the
asserted -IACK signal is to inform the DUART that the
very next cycle will be an “IACK” or “Interrupt
Acknowledge” cycle. DUART, in response to the -IACK
signal, will place the contents of the Interrupt Vector
Register (IVR) on the Data Bus. This data will be read by
the CPU, and program control will be branched to the
appropriate interrupt service routine. In the case of the
Z-80 CPU, this location is a 16 bit address which is
determined from
Table 13.
Most Significant Byte
Least Significant Byte
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Contents of the I Register (within the CPU)
The 7 Most Significant Bits within the Interrupt Vector
Register of the DUART
0
Note:
The LSB of the IVR is always set to “0” once read by the CPU. Interrupt Service Routines must begin at even ddresses.
Table 13. The Relationship between the Contents of the Interrupt Vector Register (of the DUART)
and the location of the Interrupt Service Routine (Z-80 CPU)
Additionally, the user must be aware of the contents that he/she loads into the I Register of the CPU, during run time.
-INTA
to lower priority
peripheral
Address
Decoder
Circuitry
A0 - A15
A0 - A3
D0 - D7
-CS
CS_DUART
-INTR
-INT
-WR
-RD
-MREQ
-IORQ
M1
-WR
-RD
-MEMW
-IACK
Z80 CPU
XR88C681
-MEMR
IEI
IEO
from Vcc or higher
priority peripheral
Figure 19. Schematic of an Approach to Interface the DUART to the Z-80
CPU (for Z-Mode Operation)
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