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參數(shù)資料
| 型號： | XR88C681P/40-F |
| 廠商： | Exar Corporation |
| 文件頁數(shù)： | 89/101頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC UART CMOS DUAL 40PDIP |
| 標準包裝： | 9 |
| 特點： | * |
| 通道數(shù)： | 2，DUART |
| FIFO's： | 1 字節(jié)，3 字節(jié) |
| 電源電壓： | 4.75 V ~ 5.25 V |
| 帶并行端口： | 是 |
| 帶CMOS： | 是 |
| 安裝類型： | 通孔 |
| 封裝/外殼： | 40-DIP（0.600"，15.24mm） |
| 供應商設備封裝： | 40-PDIP |
| 包裝： | 管件 |
| 其它名稱： | 1016-1640 XR88C681P/40-F-ND |
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XR88C681
88
Rev. 2.11
H.3 Standby Mode
The DUART may be placed in a standby mode to
conserve power when its operation is not required. Upon
reset, the DUART will be in the “ACTIVE OPERATION”
mode. A “SET STANDBY MODE” command issued via
the channel A Command Register disables all clocks on
the device except for the crystal oscillator, which
significantly reduces the operating current. In this mode
that only functions which will operate correctly are reading
the input port, writing the output port and the “SET
ACTIVE MODE” command. The latter, also invoked via
the Channel A Command register, restores the device to
normal operation within 25 s. Resetting the transmitters
and receivers and writing 00h into the IMR (Interrupt Mask
Register) before going into the Standby mode is
recommended to prevent any spurious interrupts from
being generated. The chip should be reprogrammed after
the “SET ACTIVE MODE” command since register
contents are not guaranteed to remain stable during the
standby mode. Active operation can also be restored via
hardware reset.
I. COMMENTS ABOUT THE XR88C681 IN 28 PIN
DIP PACKAGE
Much of this data sheet discussed features which are
available to the DUARTs which are packaged in the 40 pin
DIP or the 44 pin PLCC. However, because of the
reduced number of pins the DUARTs in the 28 pin
package do not have the following features.
D
Cannot operate in the Z-Mode
This is due to lack of the -IACK, IEI, and IEO pins
D
Cannot perform modem shaking functions
This is due to the lack of any CTS pins
J. PROGRAMMING
Operation of the DUART is programmed by writing control
words into the appropriate registers, while operational
feedback is provided by status registers which can be read
by the CPU. Register addressing is shown in .
A hardware reset clears the contents of the SRn, IMR,
ISR, OPR, and OPCR registers and initializes the IVR to
0F16. During operation, care should be exercised if the
contents of control registers are to be changed, since
certain changes may result in improper operation.
For Example:
Changing the number of bits per character while data is
being received may result in reception of erroneous
character. In general, changes to registers which control
receiver or transmitter operation should be made only
while the transmitter or receiver are disabled, and certain
changes to the ACR should be made only when the C/T is
stopped.
Mode, command, clock select, and status registers are
duplicated for each channel to provide total independent
operation.
Table 29 through Table 41 summarizes the bit
assignments for each register.
REGISTER SUMMARY
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Rx RTS
Control
Rx Int Select
Error Mode
Parity Mode
Select
Parity
Select
Number of Bits/Char.
0 = No
1 = Yes
0=RXRDY
1=FFULL
0= Char.
1= Block
00 = With Parity
01 = Force Parity
10 = No Parity
11 = Multi-Drop Mode
0 = Even
1 = Odd
00 = 5
01 = 6
10 = 7
11 = 8
Table 29. Mode Registers 1: MR1A, MR1B
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