參數(shù)資料
型號(hào): XRT86VL34_07
廠商: Exar Corporation
元件分類: 通信及網(wǎng)絡(luò)
英文描述: Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
中文描述: Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
文件頁數(shù): 109/175頁
文件大小: 904K
代理商: XRT86VL34_07
XRT86VL34
104
REV. V1.2.0
QUAD T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION
3
LCV Int Status
RUR/
WC
0
Line Code Violation Interrupt Status
.
This Reset-Upon-Read bit field indicates whether or not the Receive E1 LIU
block has detected a Line Code Violation interrupt since the last read of this
register.
0 = Indicates that the Line Code Violation interrupt has not occurred since
the last read of this register.
1 = Indicates that the Line Code Violation interrupt has occurred since the
last read of this register.
2
Rx OOF State
Change
RUR/
WC
0
Change in Out of Frame Defect Condition Interrupt Status
.
This Reset-Upon-Read bit field indicates whether or not the “Change in
Receive Out of Frame Defect Condition” interrupt has occurred since the
last read of this register.
Out of Frame defect condition is declared when “FASC” number of consecu-
tive errored FAS patterns are detected, where “FASC” indicates the Loss of
FAS Alignment Criteria in the Framing Control Register (0xn10B), bit 2-0.
If this interrupt is enabled, then the Receive E1 Framer block will generate
an interrupt in response to either one of the following conditions.
1.
Whenever the Receive E1 Framer block declares the Out of Frame
defect condition.
2.
Whenever the Receive E1 Framer block clears the Out of Frame
defect condition
0 = Indicates that the “Change in Receive Out of Frame defect condition”
interrupt has not occurred since the last read of this register
1 = Indicates that the “Change in Receive Out of Frame defect condition”
interrupt has occurred since the last read of this register
1
RxAIS State
Change
RUR/
WC
0
Change in Receive AIS Condition Interrupt Status
.
This Reset-Upon-Read bit field indicates whether or not the “Change in
Receive AIS Condition” interrupt has occurred since the last read of this reg-
ister.
If this interrupt is enabled, then the Receive E1 Framer block will generate
an interrupt in response to either one of the following conditions.
1.
Whenever the Receive E1 Framer block declares the AIS condition.
2.
Whenever the Receive E1 Framer block clears the AIS condition
0 = Indicates that the “Change in Receive AIS condition” interrupt has not
occurred since the last read of this register
1 = Indicates that the “Change in Receive AIS condition” interrupt has
occurred since the last read of this register
T
ABLE
94: A
LARM
& E
RROR
I
NTERRUPT
S
TATUS
R
EGISTER
(AEISR) H
EX
A
DDRESS
: 0
X
nB02
B
IT
F
UNCTION
T
YPE
D
EFAULT
D
ESCRIPTION
-O
PERATION
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