參數(shù)資料
型號(hào): XRT86VL34_07
廠商: Exar Corporation
元件分類: 通信及網(wǎng)絡(luò)
英文描述: Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
中文描述: Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
文件頁數(shù): 137/175頁
文件大小: 904K
代理商: XRT86VL34_07
XRT86VL34
132
REV. V1.2.0
QUAD T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION
T
ABLE
107: E
XCESSIVE
Z
ERO
E
NABLE
R
EGISTER
(EXZER) H
EX
A
DDRESS
: 0
X
nB0F
B
IT
F
UNCTION
T
YPE
D
EFAULT
D
ESCRIPTION
-O
PERATION
1
SA7_EQ_0_ENB
R/W
0
Change in “Sa 7 Equals 0” Interrupt Enable
This bit enables or disables the “Change in Sa7 Equals 0” interrupt
within the Receive E1 Framer.
If this interrupt is enabled, then the Receive E1 Framer block will
generate an interrupt in response to either one of the following
conditions.
1.
Whenever the Receive E1 Framer block detects the Received
Sa7 equals to 0 for at least 2 out of 3 times.
2.
Whenever the Receive E1 Framer block no longer detects the
Received Sa7 equals to the 0.
0 = Disables the “Change in Sa7 Equals 0” interrupt within the E1
Receive Framer Block.
1 = Enables the “Change in Sa7 Equals 0” interrupt within the E1
Receive Framer Block.
0
EXZ_ENB
R/W
0
Change in Excessive Zero Condition Interrupt Enable
This bit enables or disables the “Change in Excessive Zero Condi-
tion” interrupt within the E1 Receive Framer.
If this interrupt is enabled, then the Receive E1 Framer block will
generate an interrupt in response to either one of the following
conditions.
1.
Whenever the Receive E1 Framer block detects the
Excessive Zero Condition.
2.
Whenever the Receive E1 Framer block clears the Excessive
Zero Condition
0 = Disables the “Change in Excessive Zero Condition” interrupt
within the Receive E1 Framer Block
1 - Enables the “Change in Excessive Zero Condition” interrupt
within the Receive E1 Framer Block
相關(guān)PDF資料
PDF描述
XRT86VL34_1 Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
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