參數資料
型號: XRT86VL34_07
廠商: Exar Corporation
元件分類: 通信及網絡
英文描述: Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
中文描述: Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
文件頁數: 143/175頁
文件大?。?/td> 904K
代理商: XRT86VL34_07
XRT86VL34
138
REV. V1.2.0
QUAD T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION
T
ABLE
111: D
ATA
L
INK
I
NTERRUPT
E
NABLE
R
EGISTER
2 (DLIER2) H
EX
A
DDRESS
: 0
X
nB17
B
IT
F
UNCTION
T
YPE
D
EFAULT
D
ESCRIPTION
-O
PERATION
7
Reserved
-
-
Reserved
6
TxSOT ENB
R/W
0
Transmit HDLC2 Controller Start of Transmission (TxSOT)
Interrupt Enable
This bit enables or disables the “Transmit HDLC2
Controller Start of Transmission (TxSOT) “Interrupt within the
XRT86VL34 device. Once this interrupt is enabled, the Transmit
HDLC2 Controller will generate an interrupt when it has started to
transmit a data link message.
0 = Disables the Transmit HDLC2 Controller Start of Transmission
(TxSOT) interrupt.
1 = Enables the Transmit HDLC2 Controller Start of Transmission
(TxSOT) interrupt.
5
RxSOT ENB
R/W
0
Receive HDLC2 Controller Start of Reception (RxSOT) Interrupt
Enable
This bit enables or disables the “Receive HDLC2
Controller Start of Reception (RxSOT) “Interrupt within the
XRT86VL34 device. Once this interrupt is enabled, the Receive
HDLC2 Controller will generate an interrupt when it has started to
receive a data link message.
0 = Disables the Receive HDLC2 Controller Start of Reception
(RxSOT) interrupt.
1 = Enables the Receive HDLC2 Controller Start of Reception
(RxSOT) interrupt.
4
TxEOT ENB
R/W
0
Transmit HDLC2 Controller End of Transmission (TxEOT) Inter-
rupt Enable
This bit enables or disables the “Transmit HDLC2
Controller End of Transmission (TxEOT) “Interrupt within the
XRT86VL34 device. Once this interrupt is enabled, the Transmit
HDLC2 Controller will generate an interrupt when it has finished
transmitting a data link message.
0 = Disables the Transmit HDLC2 Controller End of Transmission
(TxEOT) interrupt.
1 = Enables the Transmit HDLC2 Controller End of Transmission
(TxEOT) interrupt.
3
RxEOT ENB
R/W
0
Receive HDLC2 Controller End of Reception (RxEOT) Interrupt
Enable
This bit enables or disables the “Receive HDLC2
Controller End of Reception (RxEOT) “Interrupt within the
XRT86VL34 device. Once this interrupt is enabled, the Receive
HDLC2 Controller will generate an interrupt when it has finished
receiving a complete data link message.
0 = Disables the Receive HDLC2 Controller End of Reception
(RxEOT) interrupt.
1 = Enables the Receive HDLC2 Controller End of Reception
(RxEOT) interrupt.
相關PDF資料
PDF描述
XRT86VL34_1 Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
XRT86VL34 Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
XRT86VL34_2 Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
XRT86VL34IB Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
XRT86VL38_2 Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
相關代理商/技術參數
參數描述
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XRT86VL34IB-F 功能描述:網絡控制器與處理器 IC 4-Ch T1/E1/J1 RoHS:否 制造商:Micrel 產品:Controller Area Network (CAN) 收發(fā)器數量: 數據速率: 電源電流(最大值):595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
XRT86VL38 制造商:EXAR 制造商全稱:EXAR 功能描述:OCTAL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION
XRT86VL38_07 制造商:EXAR 制造商全稱:EXAR 功能描述:OCTAL T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION