參數(shù)資料
型號: XRT86VL34_07
廠商: Exar Corporation
元件分類: 通信及網(wǎng)絡
英文描述: Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
中文描述: Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
文件頁數(shù): 93/175頁
文件大小: 904K
代理商: XRT86VL34_07
XRT86VL34
88
REV. V1.2.0
QUAD T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION
T
ABLE
68: R
ECEIVE
S
UBSTITUTION
S
IGNALING
R
EGISTER
0-31 (RSSR 0-31) H
EX
A
DDRESS
0
X
n3C0
TO
0
XN
3DF
B
IT
F
UNCTION
T
YPE
D
EFAULT
D
ESCRIPTION
-O
PERATION
6
SIG2-A
R/W
0
2-code signaling A
This bit provides the value of signaling bit A to substitute the receive
signaling bit A on a per channel basis when 2-code signaling substi-
tution is enabled. Register address 0xn3C0 represents time slot 0,
and 0xn3DF represents time slot 31.
5
SIG4-B
R/W
0
4-code signaling B
This bit provides the value of signaling bit B to substitute the receive
signaling bit B when 4-code signaling substitution is enabled. Regis-
ter address 0xn3C0 represents time slot 0, and 0xn3DF represents
time slot 31.
4
SIG4-A
R/W
0
4-code signaling A
This bit provides the value of signaling bit A to substitute the receive
signaling bit A when 4-code signaling substitution is enabled. Regis-
ter address 0xn3C0 represents time slot 0, and 0xn3DF represents
time slot 31.
3
SIG16-D
R/W
0
16-code signaling D
This bit provides the value of signaling bit D to substitute the receive
signaling bit D when 16-code signaling substitution is enabled. Reg-
ister address 0xn3C0 represents time slot 0, and 0xn3DF repre-
sents time slot 31.
2
SIG16-C
R/W
0
16-code signaling C
This bit provides the value of signaling bit C to substitute the receive
signaling bit C when 16-code signaling substitution is enabled. Reg-
ister address 0xn3C0 represents time slot 0, and 0xn3DF repre-
sents time slot 31.
1
SIG16-B
R/W
0
16-code signaling B
This bit provides the value of signaling bit B to substitute the receive
signaling bit B when 16-code signaling substitution is enabled. Reg-
ister address 0xn3C0 represents time slot 0, and 0xn3DF repre-
sents time slot 31.
0
SIG16-A
R/W
0
16-code signaling A
This bit provides the value of signaling bit A to substitute the receive
signaling bit A when 16-code signaling substitution is enabled. Reg-
ister address 0xn3C0 represents time slot 0, and 0xn3DF repre-
sents time slot 31.
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PDF描述
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