參數(shù)資料
型號： XRT86VL34_07
廠商： Exar Corporation
元件分類： 通信及網(wǎng)絡(luò)
英文描述： Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
中文描述： Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
文件頁數(shù)： 56/175頁
文件大?。?/td> 904K
代理商： XRT86VL34_07
XRT86VL34
51
QUAD T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION
REV. V1.2.0
T
ABLE
30: R
ECEIVE
I
NTERFACE
C
ONTROL
R
EGISTER
(RICR) H
EX
A
DDRESS
: 0
XN
122
B
IT
F
UNCTION
T
YPE
D
EFAULT
D
ESCRIPTION
-O
PERATION
7
RxSyncFrD
R/W
0
Receive Synchronous fraction data interface
This bit selects whether RxCHCLK or RxSERCLK will be used for fractional
data output if receive fractional interface is enabled. If RxSERCLK is selected
to clock out fractional data, RxCHCLK will be used as an enable signal
0 = Fractional data Is clocked out of the chip using RxChCLK if the receive
fractional interface is enabled.
1 = Fractional data is clocked out of the chip using RxSerClk if the receive
fractional interface is enabled. RxChClk is used as fractional data enable.
N
OTE
:
The Time Slot Identifier Pins (RxChn[4:0]) still indicates the time slot
number if the receive fractional data interface is not enabled.
Fractional Interface can be enabled by setting RxFr2048 to 1
6
Reserved
-
-
Reserved
5
RxPLClkEnb
R/W
0
Receive payload clock enable
This bit configures the E1 framer to either output a regular clock or a payload
clock on the receive serial clock (RxSERCLK) pin when RxSERCLK is config-
ured to be an output.
0 = Configures the framer to output a 2.048MHz clock on the RxSERCLK pin
when RxSERCLK is configured as an output.
1 = Configures the framer to output a 2.048MHz clock on the RxSERCLK pin
when receiving payload bits. There will be gaps on the RxSERCLK output pin
when receiving overhead bits.
4
RxFr2048
R/W
0
Receive Fractional/Signaling Interface Enabled
This bit is used to enable or disable the receive fractional output interface,
receive signaling output, the serial channel number output, as well as the
8kHz and the received recovered clock output. This bit only functions when
the device is configured in non-high speed or multiplexed modes of opera-
tions.
If the device is configured in base rate:
0 = configure the 5 time slot identifier pins (RxChn[4:0]) to output the channel
number in parallel as usual.
1 = configure the 5 time slot identifier pins (RxChn[4:0]) into the following dif-
ferent functions:
RxChn[0] becomes the Receive Serial SIgnaling output pin (RxSIG_n) for sig-
naling outputs. Signaling data can now be output to the RxSIG pin if config-
ured appropriately.
RxChn[1] becomes the Receive Fractional Data Output pin (RxFrTD_n) for
fractional data output. Fractional data can now be output to the RxFrTD pin if
configured appropriately.
RxChn[2] outputs the serial channel number
RxChn[3] outputs an 8kHz clock signal.
RxCHN[4] outputs the received recovered clock signal (2.048MHz for E1)
N
OTE
:
This bit has no function in the high speed or multiplexed modes of
operation. In high-speed or multiplexed modes, RxCHN[0] outputs the
Signaling data and RxCHN[4] outputs the recovered clock.
相關(guān)PDF資料
PDF描述
XRT86VL34_1 Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
XRT86VL34 Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
XRT86VL34_2 Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
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XRT86VL38_2 Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
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