參數(shù)資料
型號: XRT86VL34_07
廠商: Exar Corporation
元件分類: 通信及網(wǎng)絡(luò)
英文描述: Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
中文描述: Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
文件頁數(shù): 168/175頁
文件大?。?/td> 904K
代理商: XRT86VL34_07
XRT86VL34
163
QUAD T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION
REV. V1.2.0
T
ABLE
131: LIU G
LOBAL
C
ONTROL
R
EGISTER
0 (LIUGCR0) H
EX
A
DDRESS
: 0
X
0FE0
B
IT
F
UNCTION
T
YPE
D
EFAULT
D
ESCRIPTION
-O
PERATION
7
SR
R/W
0
Single Rail mode
This bit must set to "1" for Single Rail mode to use LIU diagnotic fea-
tures. The Framer section must be programmed as well in Register
0xn101.
0 - Dual Rail
1 - Single Rail
6
ATAOS
R/W
0
Automatic Transmit All Ones Upon RLOS:
This bit enables automatic transmission of All Ones Pattern upon
detecting the Receive Loss of Signal (RLOS) condition.
Once this bit is enabled, the Transmit E1 Framer Block will automat-
ically transmit an All “Ones” data to the line for the channel that
detects an RLOS condition.
0 = Disables the “Automatic Transmit All Ones” feature upon detect-
ing RLOS
1 = Enables the “Automatic Transmit All Ones” feature upon detect-
ing RLOS
5
RCLKE
R/W
0
Receive Clock Data (Framer Bypass mode)
0 = RPOS/RNEG data is updated on the rising edge of RCLK
1 = RPOS/RNEG data is updated on the falling edge of RCLK
4
TCLKE
R/W
0
Transmit Clock Data (Framer Bypass mode)
0 = TPOS/TNEG data is sampled on the falling edge of TCLK
1 = TPOS/TNEG data is sampled on the rising edge of TCLK
3
DATAP
R/W
0
Data Polarity
0 = Transmit input and receive output data is active “High”
1 = Transmit input and receive output data is active “Low”
2
Reserved
This Bit Is Not Used
相關(guān)PDF資料
PDF描述
XRT86VL34_1 Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
XRT86VL34 Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
XRT86VL34_2 Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
XRT86VL34IB Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
XRT86VL38_2 Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
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