參數(shù)資料
型號: XRT86VL34_07
廠商: Exar Corporation
元件分類: 通信及網(wǎng)絡
英文描述: Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
中文描述: Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
文件頁數(shù): 122/175頁
文件大?。?/td> 904K
代理商: XRT86VL34_07
XRT86VL34
117
QUAD T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION
REV. V1.2.0
T
ABLE
100: S
LIP
B
UFFER
I
NTERRUPT
S
TATUS
R
EGISTER
(SBISR) H
EX
A
DDRESS
: 0
X
nB08
B
IT
F
UNCTION
T
YPE
D
EFAULT
D
ESCRIPTION
-O
PERATION
7
TxSB_FULL
RUR/
WC
0
Transmit Slip buffer Full Interrupt Status
This Reset-Upon-Read bit indicates whether or not the Transmit Slip
Buffer Full interrupt has occurred since the last read of this register. The
transmit Slip Buffer Full interrupt is declared when the transmit slip buffer
is filled. If the transmit slip buffer is full and a WRITE operation occurs,
then a full frame of data will be deleted, and this interrupt bit will be set to
‘1’.
0 = Indicates that the Transmit Slip Buffer Full interrupt has not occurred
since the last read of this register.
1 = Indicates that the Transmit Slip Buffer Full interrupt has occurred since
the last read of this register.
6
TxSB_EMPT
RUR/
WC
0
Transmit Slip buffer Empty Interrupt Status
This Reset-Upon-Read bit indicates whether or not the Transmit Slip
Buffer Empty interrupt has occurred since the last read of this register. The
transmit Slip Buffer Empty interrupt is declared when the transmit slip
buffer is emptied. If the transmit slip buffer is emptied and a READ opera-
tion occurs, then a full frame of data will be repeated, and this interrupt bit
will be set to ‘1’.
0 = Indicates that the Transmit Slip Buffer Empty interrupt has not
occurred since the last read of this register.
1 = Indicates that the Transmit Slip Buffer Empty interrupt has occurred
since the last read of this register.
5
TxSB_SLIP
RUR/
WC
0
Transmit Slip Buffer Slips Interrupt Status
This Reset-Upon-Read bit indicates whether or not the Transmit Slip
Buffer Slips interrupt has occurred since the last read of this register. The
transmit Slip Buffer Slips interrupt is declared when the transmit slip buffer
is either filled or emptied. This interrupt bit will be set to ‘1’ in either one of
these two conditions:
1.
If the transmit slip buffer is emptied and a READ operation occurs,
then a full frame of data will be repeated, and this interrupt bit will be
set to ‘1’.
2.
If the transmit slip buffer is full and a WRITE operation occurs, then
a full frame of data will be deleted, and this interrupt bit will be set to
‘1’.
0 = Indicates that the Transmit Slip Buffer Slips interrupt has not occurred
since the last read of this register.
1 = Indicates that the Transmit Slip Buffer Slips interrupt has occurred
since the last read of this register.
N
OTE
:
Users still need to read the Transmit Slip Buffer Empty Interrupt (bit
6 of this register) or the Transmit Slip Buffer Full Interrupts (bit 7 of
this register) to determine whether transmit slip buffer empties or
fills.
相關PDF資料
PDF描述
XRT86VL34_1 Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
XRT86VL34 Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
XRT86VL34_2 Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
XRT86VL34IB Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
XRT86VL38_2 Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
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XRT86VL38 制造商:EXAR 制造商全稱:EXAR 功能描述:OCTAL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION
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