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參數(shù)資料
| 型號(hào)： | 28F004B3 |
| 廠商： | Intel Corp. |
| 英文描述： | 3 Volt Advanced Boot Block Flash Memory(3 V,4M位高級(jí)引導(dǎo)塊閃速存儲(chǔ)器) |
| 中文描述： | 3伏高級(jí)啟動(dòng)塊閃存（3伏，4分位高級(jí)引導(dǎo)塊閃速存儲(chǔ)器） |
| 文件頁(yè)數(shù)： | 14/53頁(yè) |
| 文件大?。?/td> | 300K |
| 代理商： | 28F004B3 |
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28F004/400B3, 28F008/800B3, 28F016/160B3, 28F320B3
E
14
PRELIMINARY
When V
PP
< V
PPLK
, the device will only execute the
following commands successfully: Read Array,
Read Status Register, Clear Status Register and
Read Identifier. The device provides standard
EEPROM read, standby and output disable
operations. Manufacturer identification and device
identification data can be accessed through the
CUI. All functions associated with altering memory
contents,
namely
program
accessible via the CUI. The internal Write State
Machine (WSM) completely automates program
and erase operations while the CUI signals the start
of an operation and the status register reports
status. The CUI handles the WE# interface to the
data and address latches, as well as system status
requests during WSM operation.
and
erase,
are
3.1
Bus Operation
3 Volt Advanced Boot Block flash memory devices
read, program and erase in-system via the local
CPU or microcontroller. All bus cycles to or from the
flash memory conform to standard microcontroller
bus cycles. Four control pins dictate the data flow in
and out of the flash component: CE#, OE#, WE#
and RP#. These bus operations are summarized in
Table 3.
Table 3. Bus Operations
(1)
Mode
Note
RP#
CE#
OE#
WE#
DQ
0
–7
DQ
8–15
Read (Array, Status, or
Identifier)
2
–4
V
IH
V
IL
V
IL
V
IH
D
OUT
D
OUT
Output Disable
2
V
IH
V
IL
V
IH
V
IH
High Z
High Z
Standby
2
V
IH
V
IH
X
X
High Z
High Z
Reset
2, 7
V
IL
X
X
X
High Z
High Z
Write
2, 5–7
V
IH
V
IL
V
IH
V
IL
D
IN
D
IN
NOTES:
1.
2.
3.
4.
5.
6.
7.
8-bit devices use only DQ[0:7], 16-bit devices use DQ[0:15].
X must be V
IL
, V
IH
for control pins and addresses.
See DC Characteristicsfor V
PPLK
, V
PP1
, V
PP2
, V
PP3
, V
PP4
voltages.
Manufacturer and device codes may also be accessed in read identifier mode (A
1
–A
21
= 0). See Table 5.
Refer to Table 6 for valid D
IN
during a write operation.
To program or erase the lockable blocks, hold WP# at V
IH
.
RP# must be at GND
±
0.2 V to meet the maximum deep power-down current specified.
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|---|---|
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| 28F004B5 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SMART 5 BOOT BLOCK. FLASH MEMORY FAMILY 2. 4. 8 MBIT |
| 28F004BE-T/B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:4-MBIT (256K X 16. 512K X 8) SmartVoltage BOOT BLOCK FLASH MEMORY FAMILY |
| 28F004BL-B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:4-MBlT (256K x 16. 512K x 8) LOW-POWER BOOT BLOCK FLASH MEMORY FAMILY |
| 28F004BL-T | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:4-MBlT (256K x 16. 512K x 8) LOW-POWER BOOT BLOCK FLASH MEMORY FAMILY |
| 28F004BV | 制造商:未知廠家 制造商全稱:未知廠家 功能描述: |
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