LPC Interface Bridge Registers (D31:F0)
9-14
Intel
82801BA ICH2 Datasheet
9.1.24
RTC_CONF—RTC Configuration Register (LPC I/F—D31:F0)
Offset Address:
Default Value:
Lockable:
D8h
00h
Yes
Attribute:
Size:
Power Well:
R/W
8-bit
Core
9.1.25
COM_DEC—LPC I/F Communication Port Decode Ranges
(LPC I/F—D31:F0)
Offset Address:
Default Value:
Lockable:
E0h
00h
No
Attribute:
Size:
Power Well:
R/W
8-bit
Core
Bit
Description
7:5
Reserved.
4
Upper 128-byte Lock (U128LOCK)
—R/W (special).
1 = Lock reads and writes to bytes 38h–3Fh in the upper 128 byte bank of the RTC CMOS RAM.
Write cycles to this range will have no effect and read cycles will not return any particular
guaranteed value. This is a write once register that can only be reset by a hardware reset.
0 = Access to these bytes in the upper CMOS RAM range have not been locked.
3
Lower 128-byte Lock (L128LOCK)
—R/W (special).
1 = Locks reads and writes to bytes 38h–3Fh in the lower 128 byte bank of the RTC CMOS RAM.
Write cycles to this range will have no effect and read cycles will not return any particular
guaranteed value. This is a write once register that can only be reset by a hardware reset.
0 = Access to these bytes in the lower CMOS RAM range have not been locked.
2
Upper 128-byte Enable (U128E)
—R/W.
1 = Enables access to the upper 128 byte bank of RTC CMOS RAM.
0 = Disable.
1:0
Reserved.
Bit
Description
7
Reserved
6:4
COMB Decode Range
—R/W. This field determines which range to decode for the COMB Port.
000 = 3F8h–3FFh (COM1)
001 = 2F8h–2FFh (COM2)
010 = 220h–227h
011 = 228h–22Fh
100 = 238h–23Fh
101 = 2E8h–2EFh (COM4)
110 = 338h–33Fh
111 = 3E8h–3EFh (COM3)
3
Reserved
2:0
COMA Decode Range
—R/W. This field determines which range to decode for the COMA Port.
000 = 3F8h–3FFh (COM1)
001 = 2F8h–2FFh (COM2)
010 = 220h–227h
011 = 228h–22Fh
100 = 238h–23Fh
101 = 2E8h–2EFh (COM4)
110 = 338h–33Fh
111 = 3E8h–3EFh (COM3)
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