Intel
82801BA ICH2 Datasheet
9-61
LPC Interface Bridge Registers (D31:F0)
9.8.3.2
PM1_EN—Power Management 1 Enable Register
I/O Address:
PMBASE + 02h
(
ACPI PM1a_EVT_BLK + 2)
0000h
No
Bits 0–7: Core,
Bits 8–15: Resume
Attribute:
Size:
Usage:
R/W
16-bit
ACPI or Legacy
Default Value:
Lockable:
Power Well:
7:6
Reserved
5
Global Status (GBL _STS)
—R/WC.
1 = Set when an SCI is generated due to BIOS wanting the attention of the SCI handler. BIOS has
a corresponding bit, BIOS_RLS, which will cause an SCI and set this bit.
0 = The SCI handler should then clear this bit by writing a 1 to the bit location.
4:1
Reserved
0
Timer Overflow Status (TMROF_STS)
—R/WC.
1 = This bit gets set any time bit 22 of the 24-bit timer goes high (bits are numbered from 0 to 23).
This will occur every 2.3435 seconds. When the TMROF_EN bit is set, then the setting of the
TMROF_STS bit will additionally generate an SCI or SMI# (depending on the SCI_EN).
0 = The SCI or SMI# handler clears this bit by writing a 1 to the bit location.
Bit
Description
Bit
Description
15:11
Reserved.
10
RTC Event Enable (RTC_EN)
—R/W. This bit is in the RTC well to allow an RTC event to wake after
a power failure. This bit is not cleared by any reset other than RTCRST# or a Power Button Override
event.
1 = An SCI (or SMI#) or wake event will occur when this bit is set and the RTC_STS bit goes
active.
0 = No SCI (or SMI#) or wake event is generated then RTC_STS goes active.
8
Power Button Enable (PWRBTN_EN)
—R/W.
This bit is used to enable the setting of the
PWRBTN_STS bit to generate a power management event (SMI#, SCI). PWRBTN_EN has no
effect on the PWRBTN_STS bit being set by the assertion of the power button. The Power Button is
always enabled as a Wake event.
0 = Disable.
1 = Enable.
5
Global Enable (GBL_EN)
—R/W. When both the GBL_EN and the GBL_STS are set, an SCI is
raised.
0 = Disable.
1 = Enable SCI on GBL_STS going active.
0
Timer Overflow Interrupt Enable (TMROF_EN)
—R/W. Works in conjunction with the SCI_EN bit
as described below:
TMROF_EN
SCI_EN
Effect when TMROF_STS is set
0
x
No SMI# or SCI
1
0
SMI#
1
1
SCI
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