Intel
82801BA ICH2 Datasheet
13-9
AC’97 Audio Controller Registers (D31:F5)
13.2.1
x
_BDBAR—Buffer Descriptor Base Address Register
I/O Address:
NABMBAR + 00h (PIBDBAR), Attribute:
NABMBAR + 10h (POBDBAR),
NABMBAR + 20h (MCBDBAR)
00000000h
No
R/W
Default Value:
Lockable:
Size:
Power Well:
32 bits
Core
Table 13-3. Native Audio Bus Master Control Registers
Offset
Mnemonic
Name
Default
Access
00h
PI_BDBAR
PCM In Buffer Descriptor list Base Address Register
00000000h
R/W
04h
PI_CIV
PCM In Current Index Value
00h
RO
05h
PI_LVI
PCM In Last Valid Index
00h
R/W
06h
PI_SR
PCM In Status Register
0001h
R/W
08h
PI_PICB
PCM In Position In Current Buffer
0000h
RO
0Ah
PI_PIV
PCM In Prefetched Index Value
00h
RO
0Bh
PI_CR
PCM In Control Register
00h
R/W
10h
PO_BDBAR
PCM Out Buffer Descriptor list Base Address Register
00000000h
R/W
14h
PO_CIV
PCM Out Current Index Value
00h
RO
15h
PO_LVI
PCM Out Last Valid Index
00h
R/W
16h
PO_SR
PCM Out Status Register
0001h
R/W
18h
PO_PICB
PCM Out Position In Current Buffer
0000h
RO
1Ah
PO_PIV
PCM Out Prefetched Index Value
00h
RO
1Bh
PO_CR
PCM Out Control Register
00h
R/W
20h
MC_BDBAR
Mic. In Buffer Descriptor list Base Address Register
00000000h
R/W
24h
PM_CIV
Mic. In Current Index Value
00h
RO
25h
MC_LVI
Mic. In Last Valid Index
00h
R/W
26h
MC_SR
Mic. In Status Register
0001h
R/W
28h
MC_PICB
Mic In Position In Current Buffer
0000h
RO
2Ah
MC_PIV
Mic. In Prefetched Index Value
00h
RO
2Bh
MC_CR
Mic. In Control Register
00h
R/W
2Ch
GLOB_CNT
Global Control
00000000h
R/W
30h
GLOB_STA
Global Status
00000000h
RO
34h
ACC_SEMA
Codec Write Semaphore Register
00h
R/W
Bit
Description
31:3
Buffer Descriptor Base Address[31:3]—
R/W. These bits represent address bits 31:3. The data
should be aligned on 8 byte boundaries. Each buffer descriptor is 8 bytes long and the list can
contain a maximum of 32 entries.
2:0
Hardwired to 0.
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