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參數(shù)資料
| 型號(hào)： | 82801AA |
| 廠商： | INTEL CORP |
| 元件分類： | 外設(shè)及接口 |
| 英文描述： | 82801AB (ICH0) I/O Controller Hub |
| 中文描述： | MULTIFUNCTION PERIPHERAL, PBGA241 |
| 封裝： | BGA-241 |
| 文件頁(yè)數(shù)： | 66/462頁(yè) |
| 文件大?。?/td> | 3450K |
| 代理商： | 82801AA |
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Functional Description
5-10
Intel
82801BA ICH2 Datasheet
5.2.2.2
Bus Master Operation
As a PCI Bus Master, the ICH2 integrated LAN Controller initiates memory cycles to fetch data for
transmission or deposit received data and for accessing the memory resident control structures. The
LAN Controller performs zero wait state burst read and write cycles to the host main memory. For
bus master cycles, the LAN Controller is the initiator and the host main memory (or the PCI host
bridge, depending on the configuration of the system) is the target.
The processor provides the LAN Controller with action commands and pointers to the data buffers
that reside in host main memory. The LAN Controller independently manages these structures and
initiates burst memory cycles to transfer data to and from them. The LAN Controller uses the
Memory Read Multiple (MR Multiple) command for burst accesses to data buffers and the
Memory Read Line (MR Line) command for burst accesses to control structures. For all write
accesses to the control structure, the LAN Controller uses the Memory Write (MW) command. For
write accesses to the data structure, the LAN Controller may use either the Memory Write or
Memory Write and Invalidate (MWI) commands.
Read Accesses:
The LAN Controller performs block transfers from host system memory to
perform frame transmission on the serial link. In this case, the LAN Controller initiates zero wait
state memory read burst cycles for these accesses. The length of a burst is bounded by the system,
the LAN Controller’s internal FIFO. The length of a read burst may also be bounded by the value
of the Transmit DMA Maximum Byte Count in the Configure command. The transmit DMA
Maximum Byte Count value indicates the maximum number of transmit DMA PCI cycles that will
be completed after a LAN Controller internal arbitration.
The LAN Controller, as the initiator, drives the address lines AD[31:0], the command and byte
enable lines C/BE[3:0]#, and the control lines IRDY# and FRAME#. The LAN Controller asserts
IRDY# to support zero wait state burst cycles. The target signals the LAN Controller that valid data
is ready to be read by asserting the TRDY# signal.
Write Accesses:
The LAN Controller performs block transfers to host system memory during
frame reception. In this case, the LAN Controller initiates memory write burst cycles to deposit the
data, usually without wait states. The length of a burst is bounded by the system and the LAN
Controller’s internal FIFO threshold. The length of a write burst may also be bounded by the value
of the Receive DMA Maximum Byte Count in the configure command. The Receive DMA
Maximum Byte Count value indicates the maximum number of receive DMA PCI transfers that
will be completed before the LAN Controller internal arbitration.
The LAN Controller, as the initiator, drives the address lines AD[31:0], the command and byte
enable lines C/BE[3:0]#, and the control lines IRDY# and FRAME#. The LAN Controller asserts
IRDY# to support zero wait state burst cycles. The LAN Controller also drives valid data on
AD[31:0] lines during each data phase (from the first clock and on). The target controls the length
and signal’s completion of a data phase by deassertion and assertion of TRDY#.
Cycle Completion:
The LAN Controller completes (terminates) its initiated memory burst cycles
in the following cases:
Normal Completion:
All transaction data has been transferred to or from the target device
(for example, host main memory).
Backoff:
Latency Timer has expired and the bus grant signal (GNT#) was removed from the
LAN Controller by the arbiter, indicating that the LAN Controller has been preempted by
another bus master.
Transmit or Receive DMA Maximum Byte Count:
The LAN Controller burst has reached
the length specified in the transmit or receive DMA Maximum Byte Count field in the
Configure command block.
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相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 82801AB | 82801AB (ICH0) I/O Controller Hub |
| 82803AAMRH-R | Controller Miscellaneous - Datasheet Reference |
| 82804AA | Interface IC |
| 82805AA | Interface IC |
| 82806AA | Interface IC |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 82801AASL3Z2 | 制造商: 功能描述: 制造商:Intel 功能描述: 制造商:undefined 功能描述: |
| 82801AB | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:82801AB (ICH0) I/O Controller Hub |
| 82801BA | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel 82801BA I/O Controller Hub 2 (ICH2) and Intel 82801BAM I/O Controller Hub 2 Mobile |
| 82801BAICH2 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:PERIPHERAL (MULTIFUNCTION) CONTROLLER |
| 82801DB | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel 82801DB I/O Controller Hub 4 (ICH4) |
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