LPC Interface Bridge Registers (D31:F0)
9-16
Intel
82801BA ICH2 Datasheet
9.1.28
FWH_DEC_EN1—FWH Decode Enable 1 Register
(LPC I/F—D31:F0)
Offset Address:
Default Value:
This register determines which memory ranges will be decoded on the PCI bus and forwarded to
the FWH. The ICH2 will subtractively decode cycles on PCI unless POS_DEC_EN is set to 1.
E3h
FFh
Attribute:
Size:
R/W
8 bits
Bit
Description
7
FWH Address Range Enable (FWH_F8_EN)
—RO. Enables decoding two 512 KB FWH memory
ranges and one 128 KB memory range.
1 = Enable the following ranges for the FWH
FFF80000h–FFFFFFFFh
FFB80000h–FFBFFFFFh
000E0000h–000FFFFFh
6
FWH Address Range Enable (FWH_F0_EN)
—R/W. Enables decoding two 512 KB FWH memory
ranges.
0 = Disable.
1 = Enable the following ranges for the FWH:
FFF00000h–FFF7FFFFh
FFB00000h–FFB7FFFFh
5
FWH Address Range Enable (FWH_E8_EN)
—R/W. Enables decoding two 512 KB FWH memory
ranges.
0 = Disable.
1 = Enable the following ranges for the FWH:
FFE80000h–FFEFFFFh
FFA80000h–FFAFFFFFh
4
FWH Address Range Enable (FWH_E0_EN)
—R/W. Enables decoding two 512 KB FWH memory
ranges.
0 = Disable.
1 = Enable the following ranges for the FWH:
FFE00000h–FFE7FFFFh
FFA00000h–FFA7FFFFh
3
FWH Address Range Enable (FWH_D8_EN)
—R/W. Enables decoding two 512 KB FWH memory
ranges.
0 = Disable.
1 = Enable the following ranges for the FWH
FFD80000h–FFDFFFFFh
FF980000h–FF9FFFFFh
2
FWH Address Range Enable (FWH_D0_EN)
—R/W. Enables decoding two 512 KB FWH memory
ranges.
0 = Disable.
1 = Enable the following ranges for the FWH
FFD00000h–FFD7FFFFh
FF900000h–FF97FFFFh
1
FWH Address Range Enable (FWH_C8_EN)
—R/W. Enables decoding two 512 KB FWH memory
ranges.
0 = Disable.
1 = Enable the following ranges for the FWH
FFC80000h–FFCFFFFFh
FF880000h–FF8FFFFFh
0
FWH Address Range Enable (FWH_C0_EN)
—R/W. Enables decoding two 512 KB FWH memory
ranges.
0 = Disable.
1 = Enable the following ranges for the FWH
FFC00000h–FFC7FFFFh
FF800000h–FF87FFFFh
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